Commit 8f41d122 authored by Kefeng Wang's avatar Kefeng Wang Committed by Wei Xu
Browse files

arm64: dts: hip05: Append gpio nodes 



There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.

Signed-off-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent abf9c25d

arch/arm64/boot/dts/hisilicon/hip05.dtsi

+38 −0
Original line number Diff line number Diff line
@@ -322,5 +322,43 @@ 
			reg-io-width = <4>;

			status = "disabled";

		};



		peri_gpio0: gpio@802e0000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0x802e0000 0x0 0x10000>;

			status = "disabled";



			porta: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		peri_gpio1: gpio@802f0000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0x802f0000 0x0 0x10000>;

			status = "disabled";



			portb: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				#gpio-cells = <2>;

				snps,nr-gpios = <32>;

				reg = <0>;

				interrupt-controller;

				#interrupt-cells = <2>;

				interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;

			};

		};

	};

};

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