Commit 8f2685c9 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'memory-controller-drv-tegra-5.11-2' of... 

Merge tag 'memory-controller-drv-tegra-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.11 - Tegra SoC

There is a bigger work from Dmitry Osipenko around Tegra SoC memory
controller drivers, mostly towards adding interconnect support and
integration with devfreq.  This work touches all Tegra memory controller
drivers and also few other SoC-related parts.  It's not yet finished but
the intermediate stage seems ready to merge.

Beside that Tegra 210 memory controller got few fixes and received new
swgroups (work of Nicolin Chen).

* tag 'memory-controller-drv-tegra-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (38 commits)
  memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probe
  memory: tegra: Complete tegra210_swgroups
  memory: tegra30-emc: Continue probing if timings are missing in device-tree
  memory: tegra30-emc: Make driver modular
  memory: tegra30: Add FIFO sizes to memory clients
  memory: tegra20-emc: Add devfreq support
  memory: tegra20-emc: Remove IRQ number from error message
  memory: tegra20-emc: Factor out clk initialization
  memory: tegra20-emc: Use dev_pm_opp_set_clkname()
  memory: tegra: Correct stub of devm_tegra_memory_controller_get()
  memory: tegra20: Support interconnect framework
  memory: tegra20-emc: Continue probing if timings are missing in device-tree
  memory: tegra20-emc: Make driver modular
  memory: tegra-mc: Add interconnect framework
  memory: tegra: Add missing latency allowness entry for Page Table Cache
  memory: tegra: Remove superfluous error messages around platform_get_irq()
  memory: tegra: Use devm_platform_ioremap_resource()
  memory: tegra: Add and use devm_tegra_memory_controller_get()
  dt-bindings: host1x: Document new interconnect properties
  dt-bindings: tegra30-actmon: Document OPP and interconnect properties
  ...

Link: https://lore.kernel.org/r/20201126191241.23302-1-krzk@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0a3251a1 0e1bcf2c

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt

+25 −0
Original line number Diff line number Diff line
@@ -18,8 +18,30 @@ clock-names. See ../../clock/clock-bindings.txt for details. 
../../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - actmon

- operating-points-v2: See ../bindings/opp/opp.txt for details.

- interconnects: Should contain entries for memory clients sitting on

                 MC->EMC memory interconnect path.

- interconnect-names: Should include name of the interconnect path for each

                      interconnect entry. Consult TRM documentation for

                      information about available memory clients, see MEMORY

                      CONTROLLER section.



For each opp entry in 'operating-points-v2' table:

- opp-supported-hw: bitfield indicating SoC speedo ID mask

- opp-peak-kBps: peak bandwidth of the memory channel



Example:

	dfs_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp@12750000 {

			opp-hz = /bits/ 64 <12750000>;

			opp-supported-hw = <0x000F>;

			opp-peak-kBps = <51000>;

		};

		...

	};



	actmon@6000c800 {

		compatible = "nvidia,tegra124-actmon";

		reg = <0x0 0x6000c800 0x0 0x400>;
@@ -29,4 +51,7 @@ Example: 
		clock-names = "actmon", "emc";

		resets = <&tegra_car 119>;

		reset-names = "actmon";

		operating-points-v2 = <&dfs_opp_table>;

		interconnects = <&mc TEGRA124_MC_MPCORER &emc>;

		interconnect-names = "cpu";

	};

Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt

+68 −0
Original line number Diff line number Diff line
@@ -20,6 +20,10 @@ Required properties: 
- reset-names: Must include the following entries:

  - host1x



Each host1x client module having to perform DMA through the Memory Controller

should have the interconnect endpoints set to the Memory Client and External

Memory respectively.



The host1x top-level node defines a number of children, each representing one

of the following host1x client modules:
@@ -36,6 +40,12 @@ of the following host1x client modules: 
  - reset-names: Must include the following entries:

    - mpe



  Optional properties:

  - interconnects: Must contain entry for the MPE memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



- vi: video input



  Required properties:
@@ -113,6 +123,12 @@ of the following host1x client modules: 
	  Required properties:

	  - remote-endpoint: phandle to vi port 'endpoint' node.



  Optional properties:

  - interconnects: Must contain entry for the VI memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



- epp: encoder pre-processor



  Required properties:
@@ -126,6 +142,12 @@ of the following host1x client modules: 
  - reset-names: Must include the following entries:

    - epp



  Optional properties:

  - interconnects: Must contain entry for the EPP memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



- isp: image signal processor



  Required properties:
@@ -139,6 +161,12 @@ of the following host1x client modules: 
  - reset-names: Must include the following entries:

    - isp



  Optional properties:

  - interconnects: Must contain entry for the ISP memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



- gr2d: 2D graphics engine



  Required properties:
@@ -152,6 +180,12 @@ of the following host1x client modules: 
  - reset-names: Must include the following entries:

    - 2d



  Optional properties:

  - interconnects: Must contain entry for the GR2D memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



- gr3d: 3D graphics engine



  Required properties:
@@ -170,6 +204,12 @@ of the following host1x client modules: 
    - 3d

    - 3d2 (Only required on SoCs with two 3D clocks)



  Optional properties:

  - interconnects: Must contain entry for the GR3D memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



- dc: display controller



  Required properties:
@@ -197,6 +237,10 @@ of the following host1x client modules: 
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection

  - nvidia,edid: supplies a binary EDID blob

  - nvidia,panel: phandle of a display panel

  - interconnects: Must contain entry for the DC memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



- hdmi: High Definition Multimedia Interface
@@ -345,6 +389,12 @@ of the following host1x client modules: 
  - reset-names: Must include the following entries:

    - vic



  Optional properties:

  - interconnects: Must contain entry for the VIC memory clients.

  - interconnect-names: Must include name of the interconnect path for each

    interconnect entry. Consult TRM documentation for information about

    available memory clients, see MEMORY CONTROLLER section.



Example:



/ {
@@ -498,6 +548,15 @@ Example: 
			resets = <&tegra_car 27>;

			reset-names = "dc";



			interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,

					<&mc TEGRA20_MC_DISPLAY0B &emc>,

					<&mc TEGRA20_MC_DISPLAY0C &emc>,

					<&mc TEGRA20_MC_DISPLAYHC &emc>;

			interconnect-names = "wina",

					     "winb",

					     "winc",

					     "cursor";



			rgb {

				status = "disabled";

			};
@@ -513,6 +572,15 @@ Example: 
			resets = <&tegra_car 26>;

			reset-names = "dc";



			interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,

					<&mc TEGRA20_MC_DISPLAY0BB &emc>,

					<&mc TEGRA20_MC_DISPLAY0CB &emc>,

					<&mc TEGRA20_MC_DISPLAYHCB &emc>;

			interconnect-names = "wina",

					     "winb",

					     "winc",

					     "cursor";



			rgb {

				status = "disabled";

			};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml

+19 −0
Original line number Diff line number Diff line
@@ -29,11 +29,23 @@ properties: 
    items:

      - const: emc



  "#interconnect-cells":

    const: 0



  nvidia,memory-controller:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      phandle of the memory controller node



  core-supply:

    description:

      Phandle of voltage regulator of the SoC "core" power domain.



  operating-points-v2:

    description:

      Should contain freqs and voltages and opp-supported-hw property, which

      is a bitfield indicating SoC speedo ID mask.



patternProperties:

  "^emc-timings-[0-9]+$":

    type: object
@@ -327,6 +339,8 @@ required: 
  - clocks

  - clock-names

  - nvidia,memory-controller

  - "#interconnect-cells"

  - operating-points-v2



additionalProperties: false
@@ -345,6 +359,7 @@ examples: 


        #iommu-cells = <1>;

        #reset-cells = <1>;

        #interconnect-cells = <1>;

    };



    external-memory-controller@7001b000 {
@@ -354,6 +369,10 @@ examples: 
        clock-names = "emc";



        nvidia,memory-controller = <&mc>;

        operating-points-v2 = <&dvfs_opp_table>;

        core-supply = <&vdd_core>;



        #interconnect-cells = <0>;



        emc-timings-0 {

            nvidia,ram-code = <3>;

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml

+5 −0
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ properties: 
  "#iommu-cells":

    const: 1



  "#interconnect-cells":

    const: 1



patternProperties:

  "^emc-timings-[0-9]+$":

    type: object
@@ -104,6 +107,7 @@ required: 
  - clock-names

  - "#reset-cells"

  - "#iommu-cells"

  - "#interconnect-cells"



additionalProperties: false
@@ -119,6 +123,7 @@ examples: 


        #iommu-cells = <1>;

        #reset-cells = <1>;

        #interconnect-cells = <1>;



        emc-timings-3 {

            nvidia,ram-code = <3>;

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt

+21 −1
Original line number Diff line number Diff line
@@ -12,18 +12,38 @@ Properties: 
  irrespective of ram-code configuration.

- interrupts : Should contain EMC General interrupt.

- clocks : Should contain EMC clock.

- nvidia,memory-controller : Phandle of the Memory Controller node.

- #interconnect-cells : Should be 0.

- operating-points-v2: See ../bindings/opp/opp.txt for details.



Optional properties:

- core-supply: Phandle of voltage regulator of the SoC "core" power domain.



Child device nodes describe the memory settings for different configurations and clock rates.



Example:



	opp_table: opp-table {

		compatible = "operating-points-v2";



		opp@36000000 {

			opp-microvolt = <950000 950000 1300000>;

			opp-hz = /bits/ 64 <36000000>;

		};

		...

	};



	memory-controller@7000f400 {

		#address-cells = < 1 >;

		#size-cells = < 0 >;

		#interconnect-cells = <0>;

		compatible = "nvidia,tegra20-emc";

		reg = <0x7000f4000 0x200>;

		reg = <0x7000f400 0x400>;

		interrupts = <0 78 0x04>;

		clocks = <&tegra_car TEGRA20_CLK_EMC>;

		nvidia,memory-controller = <&mc>;

		core-supply = <&core_vdd_reg>;

		operating-points-v2 = <&opp_table>;

	}

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