Commit 8f101aa0 authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'sunxi-clocks-for-3.20' of... 

Merge tag 'sunxi-clocks-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner clock changes for 3.20

The set of clock changes for the 3.20 merge window, with mostly:
  - Some PLL fixes for the A80 and A31
  - The MMC custom phase functions are removed, and moved over to the generic
    phase API.
  - Add the A80 MMC clocks

Some DT changes slipped here as well, to preserve bisectability.
parents b80418f3 76820fcf

Documentation/devicetree/bindings/clock/sunxi.txt

+36 −7
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ Required properties: 
	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s

	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20

	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31

	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31

	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31

	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31

	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23

	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
@@ -55,9 +55,11 @@ Required properties: 
	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31

	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23

	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13

	"allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10

	"allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10

	"allwinner,sun4i-a10-mmc-clk" - for the MMC clock

	"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80

	"allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80

	"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks

	"allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80

	"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23

	"allwinner,sun7i-a20-out-clk" - for the external output clocks

	"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
@@ -73,7 +75,9 @@ Required properties for all clocks: 
- #clock-cells : from common clock binding; shall be set to 0 except for

	the following compatibles where it shall be set to 1:

	"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",

	"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"

	"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",

	"allwinner,*-usb-clk", "allwinner,*-mmc-clk",

	"allwinner,*-mmc-config-clk"

- clock-output-names : shall be the corresponding names of the outputs.

	If the clock module only has one output, the name shall be the

	module name.
@@ -81,6 +85,10 @@ Required properties for all clocks: 
And "allwinner,*-usb-clk" clocks also require:

- reset-cells : shall be set to 1



The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:

- #reset-cells : shall be set to 1

- resets : shall be the reset control phandle for the mmc block.



For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate

dummy clocks at 25 MHz and 125 MHz, respectively. See example.
@@ -95,6 +103,14 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output 
is the normal PLL6 output, or "pll6". The second output is rate doubled

PLL6, or "pll6x2".



The "allwinner,*-mmc-clk" clocks have three different outputs: the

main clock, with the ID 0, and the output and sample clocks, with the

IDs 1 and 2, respectively.



The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output

per mmc controller. The number of outputs is determined by the size of

the address block, which is related to the overall mmc block.



For example:



osc24M: clk@01c20050 {
@@ -138,11 +154,11 @@ cpu: cpu@01c20054 { 
};



mmc0_clk: clk@01c20088 {

	#clock-cells = <0>;

	compatible = "allwinner,sun4i-mod0-clk";

	#clock-cells = <1>;

	compatible = "allwinner,sun4i-a10-mmc-clk";

	reg = <0x01c20088 0x4>;

	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

	clock-output-names = "mmc0";

	clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";

};



mii_phy_tx_clk: clk@2 {
@@ -170,3 +186,16 @@ gmac_clk: clk@01c20164 { 
	clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;

	clock-output-names = "gmac";

};



mmc_config_clk: clk@01c13000 {

	compatible = "allwinner,sun9i-a80-mmc-config-clk";

	reg = <0x01c13000 0x10>;

	clocks = <&ahb0_gates 8>;

	clock-names = "ahb";

	resets = <&ahb0_resets 8>;

	reset-names = "ahb";

	#clock-cells = <1>;

	#reset-cells = <1>;

	clock-output-names = "mmc0_config", "mmc1_config",

			     "mmc2_config", "mmc3_config";

};

Documentation/devicetree/bindings/mmc/sunxi-mmc.txt

+4 −4
Original line number Diff line number Diff line
@@ -10,8 +10,8 @@ Absolute maximum transfer rate is 200MB/s 
Required properties:

 - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"

 - reg : mmc controller base registers

 - clocks : a list with 2 phandle + clock specifier pairs

 - clock-names : must contain "ahb" and "mmc"

 - clocks : a list with 4 phandle + clock specifier pairs

 - clock-names : must contain "ahb", "mmc", "output" and "sample"

 - interrupts : mmc controller interrupt



Optional properties:
@@ -25,8 +25,8 @@ Examples: 
	mmc0: mmc@01c0f000 {

		compatible = "allwinner,sun5i-a13-mmc";

		reg = <0x01c0f000 0x1000>;

		clocks = <&ahb_gates 8>, <&mmc0_clk>;

		clock-names = "ahb", "mod";

		clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>;

		clock-names = "ahb", "mod", "output", "sample";

		interrupts = <0 32 4>;

		status = "disabled";

	};

arch/arm/boot/dts/sun4i-a10.dtsi

+52 −20
Original line number Diff line number Diff line
@@ -226,35 +226,43 @@ 
		};



		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};



		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};



		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};



		mmc3_clk: clk@01c20094 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20094 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc3";

			clock-output-names = "mmc3",

					     "mmc3_output",

					     "mmc3_sample";

		};



		ts_clk: clk@01c20098 {
@@ -398,8 +406,14 @@ 
		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>, <&mmc0_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 8>,

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <32>;

			status = "disabled";

		};
@@ -407,8 +421,14 @@ 
		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c10000 0x1000>;

			clocks = <&ahb_gates 9>, <&mmc1_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 9>,

				 <&mmc1_clk 0>,

				 <&mmc1_clk 1>,

				 <&mmc1_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <33>;

			status = "disabled";

		};
@@ -416,8 +436,14 @@ 
		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>, <&mmc2_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 10>,

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <34>;

			status = "disabled";

		};
@@ -425,8 +451,14 @@ 
		mmc3: mmc@01c12000 {

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c12000 0x1000>;

			clocks = <&ahb_gates 11>, <&mmc3_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 11>,

				 <&mmc3_clk 0>,

				 <&mmc3_clk 1>,

				 <&mmc3_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <35>;

			status = "disabled";

		};

arch/arm/boot/dts/sun5i-a10s.dtsi

+39 −15
Original line number Diff line number Diff line
@@ -211,27 +211,33 @@ 
		};



		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};



		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};



		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};



		ts_clk: clk@01c20098 {
@@ -359,8 +365,14 @@ 
		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>, <&mmc0_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 8>,

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <32>;

			status = "disabled";

		};
@@ -368,8 +380,14 @@ 
		mmc1: mmc@01c10000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c10000 0x1000>;

			clocks = <&ahb_gates 9>, <&mmc1_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 9>,

				 <&mmc1_clk 0>,

				 <&mmc1_clk 1>,

				 <&mmc1_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <33>;

			status = "disabled";

		};
@@ -377,8 +395,14 @@ 
		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>, <&mmc2_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 10>,

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <34>;

			status = "disabled";

		};

arch/arm/boot/dts/sun5i-a13.dtsi

+31 −13
Original line number Diff line number Diff line
@@ -195,27 +195,33 @@ 
		};



		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";

			clock-output-names = "mmc0",

					     "mmc0_output",

					     "mmc0_sample";

		};



		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";

			clock-output-names = "mmc1",

					     "mmc1_output",

					     "mmc1_sample";

		};



		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod0-clk";

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-mmc-clk";

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";

			clock-output-names = "mmc2",

					     "mmc2_output",

					     "mmc2_sample";

		};



		ts_clk: clk@01c20098 {
@@ -327,8 +333,14 @@ 
		mmc0: mmc@01c0f000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c0f000 0x1000>;

			clocks = <&ahb_gates 8>, <&mmc0_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 8>,

				 <&mmc0_clk 0>,

				 <&mmc0_clk 1>,

				 <&mmc0_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <32>;

			status = "disabled";

		};
@@ -336,8 +348,14 @@ 
		mmc2: mmc@01c11000 {

			compatible = "allwinner,sun5i-a13-mmc";

			reg = <0x01c11000 0x1000>;

			clocks = <&ahb_gates 10>, <&mmc2_clk>;

			clock-names = "ahb", "mmc";

			clocks = <&ahb_gates 10>,

				 <&mmc2_clk 0>,

				 <&mmc2_clk 1>,

				 <&mmc2_clk 2>;

			clock-names = "ahb",

				      "mmc",

				      "output",

				      "sample";

			interrupts = <34>;

			status = "disabled";

		};

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