net/mlx5e: TLS, Do not expose FPGA TLS counter if not supported (8f0bcd19) · Commits · 戴 / test

The set of TLS TX global SW counters in mlx5e_tls_sw_stats_desc is updated from all rings by using atomic ops. This set of stats is used only in the FPGA TLS use case, not in the Connect-X TLS one, where regular per-ring counters are used. Do not expose them in the Connect-X use case, as this would cause counter duplication. For example, tx_tls_drop_no_sync_data would appear twice in the ethtool stats. Fixes: ("net/mlx5e: Add kTLS TX HW offload support") Signed-off-by:

Tariq Toukan <tariqt@mellanox.com> Reviewed-by:

Moshe Shemesh <moshe@nvidia.com> Signed-off-by:

Saeed Mahameed <saeedm@nvidia.com>

drivers/net/ethernet/mellanox/mlx5/core/en_accel/tls_stats.c

+8 −4

Original line number	Diff line number	Diff line
		@@ -35,7 +35,6 @@
		#include <net/sock.h>

		#include "en.h"
		#include "accel/tls.h"
		#include "fpga/sdk.h"
		#include "en_accel/tls.h"

		@@ -51,9 +50,14 @@ static const struct counter_desc mlx5e_tls_sw_stats_desc[] = {

		#define NUM_TLS_SW_COUNTERS ARRAY_SIZE(mlx5e_tls_sw_stats_desc)

		static bool is_tls_atomic_stats(struct mlx5e_priv *priv)
		{
		return priv->tls && !mlx5_accel_is_ktls_device(priv->mdev);
		}

		int mlx5e_tls_get_count(struct mlx5e_priv *priv)
		{
		if (!priv->tls)
		if (!is_tls_atomic_stats(priv))
		return 0;

		return NUM_TLS_SW_COUNTERS;
		@@ -63,7 +67,7 @@ int mlx5e_tls_get_strings(struct mlx5e_priv priv, uint8_t data)
		{
		unsigned int i, idx = 0;

		if (!priv->tls)
		if (!is_tls_atomic_stats(priv))
		return 0;

		for (i = 0; i < NUM_TLS_SW_COUNTERS; i++)
		@@ -77,7 +81,7 @@ int mlx5e_tls_get_stats(struct mlx5e_priv priv, u64 data)
		{
		int i, idx = 0;

		if (!priv->tls)
		if (!is_tls_atomic_stats(priv))
		return 0;

		for (i = 0; i < NUM_TLS_SW_COUNTERS; i++)

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