Commit 8ef8f360 authored by Dave Martin's avatar Dave Martin Committed by Catalin Marinas
Browse files

arm64: Basic Branch Target Identification support 



This patch adds the bare minimum required to expose the ARMv8.5
Branch Target Identification feature to userspace.

By itself, this does _not_ automatically enable BTI for any initial
executable pages mapped by execve().  This will come later, but for
now it should be possible to enable BTI manually on those pages by
using mprotect() from within the target process.

Other arches already using the generic mman.h are already using
0x10 for arch-specific prot flags, so we use that for PROT_BTI
here.

For consistency, signal handler entry points in BTI guarded pages
are required to be annotated as such, just like any other function.
This blocks a relatively minor attack vector, but comforming
userspace will have the annotations anyway, so we may as well
enforce them.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarDave Martin <Dave.Martin@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 00e19cee

Documentation/arm64/cpu-feature-registers.rst

+2 −0
Original line number Diff line number Diff line
@@ -176,6 +176,8 @@ infrastructure: 
     +------------------------------+---------+---------+

     | SSBS                         | [7-4]   |    y    |

     +------------------------------+---------+---------+

     | BT                           | [3-0]   |    y    |

     +------------------------------+---------+---------+





  4) MIDR_EL1 - Main ID Register

Documentation/arm64/elf_hwcaps.rst

+5 −0
Original line number Diff line number Diff line
@@ -236,6 +236,11 @@ HWCAP2_RNG 


    Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.



HWCAP2_BTI



    Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001.





4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -58,7 +58,8 @@ 
#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE	48

#define ARM64_HAS_E0PD				49

#define ARM64_HAS_RNG				50

#define ARM64_BTI				51



#define ARM64_NCAPS				51

#define ARM64_NCAPS				52



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cpufeature.h

+6 −0
Original line number Diff line number Diff line
@@ -613,6 +613,12 @@ static inline bool system_has_prio_mask_debugging(void) 
	       system_uses_irq_prio_masking();

}



static inline bool system_supports_bti(void)

{

	return IS_ENABLED(CONFIG_ARM64_BTI) &&

		cpus_have_const_cap(ARM64_BTI);

}



static inline bool system_capabilities_finalized(void)

{

	return static_branch_likely(&arm64_const_caps_ready);

arch/arm64/include/asm/esr.h

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */

/* Unallocated EC: 0x0A - 0x0B */

#define ESR_ELx_EC_CP14_64	(0x0C)

/* Unallocated EC: 0x0d */

#define ESR_ELx_EC_BTI		(0x0D)

#define ESR_ELx_EC_ILL		(0x0E)

/* Unallocated EC: 0x0F - 0x10 */

#define ESR_ELx_EC_SVC32	(0x11)

CRA Git | Maintained and supported by SUSTech CRA and CCSE