Commit 8ee83b2a authored by Alexander Shishkin's avatar Alexander Shishkin Committed by Thomas Gleixner
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perf/x86/intel/pt: Add support for PTWRITE and power event tracing 



The Intel PT facility grew some new functionality:

  * PTWRITE packet carries the payload of the new PTWRITE instruction
    that can be used to instrument Intel PT traces with user-supplied
    data. Packets of this type are only generated if 'ptwrite' capability
    is set and PTWEn bit is set in the event attribute's config. Flow
    update packets (FUP) can be generated on PTWRITE packets if FUPonPTW
    config bit is set. Setting these bits is not allowed if 'ptwrite'
    capability is not set.

  * PWRE, PWRX, MWAIT, EXSTOP packets communicate core power management
    events. These depend on 'power_event_tracing' capability and are
    enabled by setting PwrEvtEn bit in the event attribute.

Extend the driver capabilities and provide the proper sanity checks in the
event validation function.

[ tglx: Massaged changelog ]

Signed-off-by: default avatarAlexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: vince@deater.net
Cc: eranian@google.com
Cc: Adrian Hunter <adrian.hunter@intel.com>
Link: http://lkml.kernel.org/r/20160916134819.1978-1-alexander.shishkin@linux.intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent cd34cd97

arch/x86/events/intel/pt.c

+23 −1
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ static struct pt_cap_desc { 
	PT_CAP(psb_cyc,			0, CR_EBX, BIT(1)),

	PT_CAP(ip_filtering,		0, CR_EBX, BIT(2)),

	PT_CAP(mtc,			0, CR_EBX, BIT(3)),

	PT_CAP(ptwrite,			0, CR_EBX, BIT(4)),

	PT_CAP(power_event_trace,	0, CR_EBX, BIT(5)),

	PT_CAP(topa_output,		0, CR_ECX, BIT(0)),

	PT_CAP(topa_multiple_entries,	0, CR_ECX, BIT(1)),

	PT_CAP(single_range_output,	0, CR_ECX, BIT(2)),
@@ -259,10 +261,16 @@ fail: 
#define RTIT_CTL_MTC	(RTIT_CTL_MTC_EN	| \

			 RTIT_CTL_MTC_RANGE)



#define RTIT_CTL_PTW	(RTIT_CTL_PTW_EN	| \

			 RTIT_CTL_FUP_ON_PTW)



#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN		| \

			RTIT_CTL_DISRETC	| \

			RTIT_CTL_CYC_PSB	| \

			RTIT_CTL_MTC)

			RTIT_CTL_MTC		| \

			RTIT_CTL_PWR_EVT_EN	| \

			RTIT_CTL_FUP_ON_PTW	| \

			RTIT_CTL_PTW_EN)



static bool pt_event_valid(struct perf_event *event)

{
@@ -311,6 +319,20 @@ static bool pt_event_valid(struct perf_event *event) 
			return false;

	}



	if (config & RTIT_CTL_PWR_EVT_EN &&

	    !pt_cap_get(PT_CAP_power_event_trace))

		return false;



	if (config & RTIT_CTL_PTW) {

		if (!pt_cap_get(PT_CAP_ptwrite))

			return false;



		/* FUPonPTW without PTW doesn't make sense */

		if ((config & RTIT_CTL_FUP_ON_PTW) &&

		    !(config & RTIT_CTL_PTW_EN))

			return false;

	}



	return true;

}

arch/x86/events/intel/pt.h

+5 −0
Original line number Diff line number Diff line
@@ -26,11 +26,14 @@ 
#define RTIT_CTL_CYCLEACC		BIT(1)

#define RTIT_CTL_OS			BIT(2)

#define RTIT_CTL_USR			BIT(3)

#define RTIT_CTL_PWR_EVT_EN		BIT(4)

#define RTIT_CTL_FUP_ON_PTW		BIT(5)

#define RTIT_CTL_CR3EN			BIT(7)

#define RTIT_CTL_TOPA			BIT(8)

#define RTIT_CTL_MTC_EN			BIT(9)

#define RTIT_CTL_TSC_EN			BIT(10)

#define RTIT_CTL_DISRETC		BIT(11)

#define RTIT_CTL_PTW_EN			BIT(12)

#define RTIT_CTL_BRANCH_EN		BIT(13)

#define RTIT_CTL_MTC_RANGE_OFFSET	14

#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
@@ -91,6 +94,8 @@ enum pt_capabilities { 
	PT_CAP_psb_cyc,

	PT_CAP_ip_filtering,

	PT_CAP_mtc,

	PT_CAP_ptwrite,

	PT_CAP_power_event_trace,

	PT_CAP_topa_output,

	PT_CAP_topa_multiple_entries,

	PT_CAP_single_range_output,

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