Commit 8ee775f9 authored by Joe Perches's avatar Joe Perches Committed by Greg Kroah-Hartman
Browse files

staging: rts5208: Remove RTSX_READ_REG and RTSX_WRITE_REG macros 



Macros with hidden flow control are bad form as the code path
taken can be unexpected for the reader.

Expand these in-place and remove the macros.

Done with coccinelle script:

@@
expression chip;
expression arg1;
expression arg2;
expression arg3;
@@

-	RTSX_WRITE_REG(chip, arg1, arg2, arg3);
+	retval = rtsx_write_register(chip, arg1, arg2, arg3);
+	if (retval) {
+		rtsx_trace(chip);
+		return retval;
+	}

@@
expression chip;
expression arg1;
expression arg2;
@@

-	RTSX_READ_REG(chip, arg1, arg2);
+	retval = rtsx_read_register(chip, arg1, arg2);
+	if (retval) {
+		rtsx_trace(chip);
+		return retval;
+	}

Signed-off-by: default avatarJoe Perches <joe@perches.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 031366ea

drivers/staging/rts5208/ms.c

+199 −51
Original line number Diff line number Diff line
@@ -169,7 +169,11 @@ static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, 
		return retval;

	}



	RTSX_READ_REG(chip, MS_TRANS_CFG, &val);

	retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) {

		rtsx_trace(chip);

		return STATUS_FAIL;
@@ -424,25 +428,71 @@ static int ms_switch_clock(struct rtsx_chip *chip) 


static int ms_pull_ctl_disable(struct rtsx_chip *chip)

{

	int retval;



	if (CHECK_PID(chip, 0x5208)) {

		RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,

		retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,

					     MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD);

		RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,

					     MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD);

		RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,

					     MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);

		RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,

					     XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);

		RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,

					     MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);

		RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF,

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,

					     MS_D5_PD | MS_D4_PD);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

	} else if (CHECK_PID(chip, 0x5288)) {

		if (CHECK_BARO_PKG(chip, QFN)) {

			RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);

			RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);

			RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);

			RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);

			retval = rtsx_write_register(chip, CARD_PULL_CTL1,

						     0xFF, 0x55);

			if (retval) {

				rtsx_trace(chip);

				return retval;

			}

			retval = rtsx_write_register(chip, CARD_PULL_CTL2,

						     0xFF, 0x55);

			if (retval) {

				rtsx_trace(chip);

				return retval;

			}

			retval = rtsx_write_register(chip, CARD_PULL_CTL3,

						     0xFF, 0x4B);

			if (retval) {

				rtsx_trace(chip);

				return retval;

			}

			retval = rtsx_write_register(chip, CARD_PULL_CTL4,

						     0xFF, 0x69);

			if (retval) {

				rtsx_trace(chip);

				return retval;

			}

		}

	}
@@ -525,8 +575,12 @@ static int ms_prepare_reset(struct rtsx_chip *chip) 
			return STATUS_FAIL;

		}

	} else {

		RTSX_WRITE_REG(chip, FPGA_PULL_CTL,

		retval = rtsx_write_register(chip, FPGA_PULL_CTL,

					     FPGA_MS_PULL_CTL_BIT | 0x20, 0);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

	}



	if (!chip->ft2_fast_mode) {
@@ -553,21 +607,40 @@ static int ms_prepare_reset(struct rtsx_chip *chip) 
#endif

	}



	RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN);

	retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,

				     MS_OUTPUT_EN);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	if (chip->asic_code) {

		RTSX_WRITE_REG(chip, MS_CFG, 0xFF,

			SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |

			NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);

		retval = rtsx_write_register(chip, MS_CFG, 0xFF,

					     SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

	} else {

		RTSX_WRITE_REG(chip, MS_CFG, 0xFF,

			SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |

			NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);

		retval = rtsx_write_register(chip, MS_CFG, 0xFF,

					     SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

	}

	retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF,

				     NO_WAIT_INT | NO_AUTO_READ_INT_REG);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR,

				     MS_STOP | MS_CLR_ERR);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	RTSX_WRITE_REG(chip, MS_TRANS_CFG,

		0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG);

	RTSX_WRITE_REG(chip, CARD_STOP,

		MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);



	retval = ms_set_init_para(chip);

	if (retval != STATUS_SUCCESS) {
@@ -601,7 +674,11 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 
		return STATUS_FAIL;

	}



	RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val);

	retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val);

	if (val != 0x01) {

		if (val != 0x02)
@@ -611,7 +688,11 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 
		return STATUS_FAIL;

	}



	RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val);

	retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val);

	if (val != 0) {

		ms_card->check_ms_flow = 1;
@@ -619,10 +700,18 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 
		return STATUS_FAIL;

	}



	RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val);

	retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val);

	if (val == 0) {

		RTSX_READ_REG(chip, PPBUF_BASE2, &val);

		retval = rtsx_read_register(chip, PPBUF_BASE2, &val);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		if (val & WRT_PRTCT)

			chip->card_wp |= MS_CARD;

		else
@@ -638,7 +727,11 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 


	ms_card->ms_type |= TYPE_MSPRO;



	RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val);

	retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val);

	if (val == 0) {

		ms_card->ms_type &= 0x0F;
@@ -753,8 +846,12 @@ static int ms_switch_8bit_bus(struct rtsx_chip *chip) 
		return STATUS_FAIL;

	}



	RTSX_WRITE_REG(chip, MS_CFG, 0x98,

	retval = rtsx_write_register(chip, MS_CFG, 0x98,

				     MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	ms_card->ms_type |= MS_8BIT;

	retval = ms_set_init_para(chip);

	if (retval != STATUS_SUCCESS) {
@@ -817,8 +914,17 @@ static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) 
	}



	/* Switch MS-PRO into Parallel mode */

	RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);

	RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);

	retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD,

				     PUSH_TIME_ODD);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	retval = ms_set_init_para(chip);

	if (retval != STATUS_SUCCESS) {
@@ -872,7 +978,11 @@ static int msxc_change_power(struct rtsx_chip *chip, u8 mode) 
		return STATUS_FAIL;

	}



	RTSX_READ_REG(chip, MS_TRANS_CFG, buf);

	retval = rtsx_read_register(chip, MS_TRANS_CFG, buf);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) {

		rtsx_trace(chip);

		return STATUS_FAIL;
@@ -1775,7 +1885,11 @@ static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 
		return STATUS_FAIL;

	}



	RTSX_READ_REG(chip, PPBUF_BASE2, &val);

	retval = rtsx_read_register(chip, PPBUF_BASE2, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	if (val & BUF_FULL) {

		retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
@@ -2070,7 +2184,11 @@ static int reset_ms(struct rtsx_chip *chip) 
		return STATUS_FAIL;

	}



	RTSX_READ_REG(chip, PPBUF_BASE2, &val);

	retval = rtsx_read_register(chip, PPBUF_BASE2, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	if (val & WRT_PRTCT)

		chip->card_wp |= MS_CARD;

	else
@@ -2238,8 +2356,16 @@ RE_SEARCH: 
			return STATUS_FAIL;

		}



		RTSX_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);

		RTSX_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);

		retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}



		retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,

					NO_WAIT_INT);
@@ -2248,8 +2374,13 @@ RE_SEARCH: 
			return STATUS_FAIL;

		}



		RTSX_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,

		retval = rtsx_write_register(chip, MS_CFG,

					     0x58 | MS_NO_CHECK_INT,

					     MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}



		ms_card->ms_type |= MS_4BIT;

	}
@@ -2869,7 +3000,11 @@ static int mspro_rw_multi_sector(struct scsi_cmnd *srb, 
	else

		trans_mode = MS_TM_AUTO_WRITE;



	RTSX_READ_REG(chip, MS_TRANS_CFG, &val);

	retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	if (ms_card->seq_mode) {

		if ((ms_card->pre_dir != srb->sc_data_direction)
@@ -3154,7 +3289,11 @@ int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 
		return STATUS_FAIL;

	}



	RTSX_READ_REG(chip, MS_TRANS_CFG, &tmp);

	retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {

		rtsx_trace(chip);
@@ -4616,10 +4755,19 @@ int ms_power_off_card3v3(struct rtsx_chip *chip) 
			return STATUS_FAIL;

		}

	} else {

		RTSX_WRITE_REG(chip, FPGA_PULL_CTL,

			FPGA_MS_PULL_CTL_BIT | 0x20, FPGA_MS_PULL_CTL_BIT);

		retval = rtsx_write_register(chip, FPGA_PULL_CTL,

					     FPGA_MS_PULL_CTL_BIT | 0x20,

					     FPGA_MS_PULL_CTL_BIT);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

	}

	retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, 0);

	if (!chip->ft2_fast_mode) {

		retval = card_power_off(chip, MS_CARD);

		if (retval != STATUS_SUCCESS) {

drivers/staging/rts5208/rtsx_card.c

+80 −16
Original line number Diff line number Diff line
@@ -698,7 +698,11 @@ int switch_ssc_clock(struct rtsx_chip *chip, int clk) 
	}



	udelay(10);

	RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);

	retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	chip->cur_clk = clk;
@@ -707,6 +711,7 @@ int switch_ssc_clock(struct rtsx_chip *chip, int clk) 


int switch_normal_clock(struct rtsx_chip *chip, int clk)

{

	int retval;

	u8 sel, div, mcu_cnt;

	int sd_vpclk_phase_reset = 0;
@@ -791,23 +796,58 @@ int switch_normal_clock(struct rtsx_chip *chip, int clk) 
		return STATUS_FAIL;

	}



	RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);

	retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	if (sd_vpclk_phase_reset) {

		RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);

		RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, 0);

		retval = rtsx_write_register(chip, SD_VPCLK0_CTL,

					     PHASE_NOT_RESET, 0);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, SD_VPCLK1_CTL,

					     PHASE_NOT_RESET, 0);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

	}

	retval = rtsx_write_register(chip, CLK_DIV, 0xFF,

				     (div << 4) | mcu_cnt);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}

	RTSX_WRITE_REG(chip, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);

	RTSX_WRITE_REG(chip, CLK_SEL, 0xFF, sel);



	if (sd_vpclk_phase_reset) {

		udelay(200);

		RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET,

				PHASE_NOT_RESET);

		RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET,

				PHASE_NOT_RESET);

		retval = rtsx_write_register(chip, SD_VPCLK0_CTL,

					     PHASE_NOT_RESET, PHASE_NOT_RESET);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		retval = rtsx_write_register(chip, SD_VPCLK1_CTL,

					     PHASE_NOT_RESET, PHASE_NOT_RESET);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		udelay(200);

	}

	RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, 0);

	retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	chip->cur_clk = clk;
@@ -842,6 +882,7 @@ void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, 


int enable_card_clock(struct rtsx_chip *chip, u8 card)

{

	int retval;

	u8 clk_en = 0;



	if (card & XD_CARD)
@@ -851,13 +892,18 @@ int enable_card_clock(struct rtsx_chip *chip, u8 card) 
	if (card & MS_CARD)

		clk_en |= MS_CLK_EN;



	RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);

	retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	return STATUS_SUCCESS;

}



int disable_card_clock(struct rtsx_chip *chip, u8 card)

{

	int retval;

	u8 clk_en = 0;



	if (card & XD_CARD)
@@ -867,7 +913,11 @@ int disable_card_clock(struct rtsx_chip *chip, u8 card) 
	if (card & MS_CARD)

		clk_en |= MS_CLK_EN;



	RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0);

	retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	return STATUS_SUCCESS;

}
@@ -912,6 +962,7 @@ int card_power_on(struct rtsx_chip *chip, u8 card) 


int card_power_off(struct rtsx_chip *chip, u8 card)

{

	int retval;

	u8 mask, val;



	if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
@@ -922,7 +973,11 @@ int card_power_off(struct rtsx_chip *chip, u8 card) 
		val = SD_POWER_OFF;

	}



	RTSX_WRITE_REG(chip, CARD_PWR_CTL, mask, val);

	retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	return STATUS_SUCCESS;

}
@@ -972,6 +1027,7 @@ int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 


int card_share_mode(struct rtsx_chip *chip, int card)

{

	int retval;

	u8 mask, value;



	if (CHECK_PID(chip, 0x5208)) {
@@ -1005,7 +1061,11 @@ int card_share_mode(struct rtsx_chip *chip, int card) 
		return STATUS_FAIL;

	}



	RTSX_WRITE_REG(chip, CARD_SHARE_MODE, mask, value);

	retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	return STATUS_SUCCESS;

}
@@ -1031,7 +1091,11 @@ int select_card(struct rtsx_chip *chip, int card) 
			return STATUS_FAIL;

		}



		RTSX_WRITE_REG(chip, CARD_SELECT, 0x07, mod);

		retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod);

		if (retval) {

			rtsx_trace(chip);

			return retval;

		}

		chip->cur_card = card;



		retval =  card_share_mode(chip, card);

drivers/staging/rts5208/rtsx_card.h

+7 −1
Original line number Diff line number Diff line
@@ -1061,7 +1061,13 @@ int card_power_off(struct rtsx_chip *chip, u8 card); 


static inline int card_power_off_all(struct rtsx_chip *chip)

{

	RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0x0F, 0x0F);

	int retval;



	retval = rtsx_write_register(chip, CARD_PWR_CTL, 0x0F, 0x0F);

	if (retval) {

		rtsx_trace(chip);

		return retval;

	}



	return STATUS_SUCCESS;

}

drivers/staging/rts5208/rtsx_chip.c

+498 −109

File changed.

Preview size limit exceeded, changes collapsed.

drivers/staging/rts5208/rtsx_chip.h

+0 −18
Original line number Diff line number Diff line
@@ -988,22 +988,4 @@ int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); 
int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);

int rtsx_check_chip_exist(struct rtsx_chip *chip);



#define RTSX_WRITE_REG(chip, addr, mask, data)				\

do {									\

	int retval = rtsx_write_register(chip, addr, mask, data);	\

	if (retval != STATUS_SUCCESS) {					\

		rtsx_trace(chip);					\

		return retval;						\

	}								\

} while (0)



#define RTSX_READ_REG(chip, addr, data)					\

do {									\

	int retval = rtsx_read_register(chip, addr, data);		\

	if (retval != STATUS_SUCCESS) {					\

		rtsx_trace(chip);					\

		return retval;						\

	}								\

} while (0)



#endif  /* __REALTEK_RTSX_CHIP_H */

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