Commit 8ed3a6b2 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a774c0: Add display output support 



The RZ/G2E (a.k.a. R8A774C0) has one RGB output and two LVDS
outputs connected to DU.
This patch add support for DU, LVDS encoders, VSP and FCP.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 47f63867

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+167 −0
Original line number Diff line number Diff line
@@ -1281,6 +1281,173 @@ 
			resets = <&cpg 408>;

		};



		vspb0: vsp@fe960000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe960000 0 0x8000>;

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 626>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 626>;

			renesas,fcp = <&fcpvb0>;

		};



		fcpvb0: fcp@fe96f000 {

			compatible = "renesas,fcpv";

			reg = <0 0xfe96f000 0 0x200>;

			clocks = <&cpg CPG_MOD 607>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 607>;

			iommus = <&ipmmu_vp0 5>;

		};



		vspi0: vsp@fe9a0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9a0000 0 0x8000>;

			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 631>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 631>;

			renesas,fcp = <&fcpvi0>;

		};



		fcpvi0: fcp@fe9af000 {

			compatible = "renesas,fcpv";

			reg = <0 0xfe9af000 0 0x200>;

			clocks = <&cpg CPG_MOD 611>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 611>;

			iommus = <&ipmmu_vp0 8>;

		};



		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x7000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 623>;

			renesas,fcp = <&fcpvd0>;

		};



		fcpvd0: fcp@fea27000 {

			compatible = "renesas,fcpv";

			reg = <0 0xfea27000 0 0x200>;

			clocks = <&cpg CPG_MOD 603>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 603>;

			iommus = <&ipmmu_vi0 8>;

		};



		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x7000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 622>;

			renesas,fcp = <&fcpvd1>;

		};



		fcpvd1: fcp@fea2f000 {

			compatible = "renesas,fcpv";

			reg = <0 0xfea2f000 0 0x200>;

			clocks = <&cpg CPG_MOD 602>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 602>;

			iommus = <&ipmmu_vi0 9>;

		};



		du: display@feb00000 {

			compatible = "renesas,du-r8a774c0";

			reg = <0 0xfeb00000 0 0x80000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>;

			clock-names = "du.0", "du.1";

			vsps = <&vspd0 0 &vspd1 0>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					du_out_rgb: endpoint {

					};

				};



				port@1 {

					reg = <1>;

					du_out_lvds0: endpoint {

						remote-endpoint = <&lvds0_in>;

					};

				};



				port@2 {

					reg = <2>;

					du_out_lvds1: endpoint {

						remote-endpoint = <&lvds1_in>;

					};

				};

			};

		};



		lvds0: lvds-encoder@feb90000 {

			compatible = "renesas,r8a774c0-lvds";

			reg = <0 0xfeb90000 0 0x20>;

			clocks = <&cpg CPG_MOD 727>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 727>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					lvds0_in: endpoint {

						remote-endpoint = <&du_out_lvds0>;

					};

				};



				port@1 {

					reg = <1>;

					lvds0_out: endpoint {

					};

				};

			};

		};



		lvds1: lvds-encoder@feb90100 {

			compatible = "renesas,r8a774c0-lvds";

			reg = <0 0xfeb90100 0 0x20>;

			clocks = <&cpg CPG_MOD 727>;

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 726>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					lvds1_in: endpoint {

						remote-endpoint = <&du_out_lvds1>;

					};

				};



				port@1 {

					reg = <1>;

					lvds1_out: endpoint {

					};

				};

			};

		};



		prr: chipid@fff00044 {

			compatible = "renesas,prr";

			reg = <0 0xfff00044 0 4>;

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