Commit 8e8e9a0b authored Nov 02, 2015 by Alexander Duyck Committed by Jeff Kirsher Dec 12, 2015

ixgbe: Fix SR-IOV VLAN pool configuration

The code for checking the PF bit in ixgbe_set_vf_vlan_msg was using the
wrong offset and as a result it was pulling the VLAN off of the PF even if
there were VFs numbered greater than 40 that still had the VLAN enabled.

Signed-off-by: Alexander Duyck <aduyck@mirantis.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

parent 530fd82a

drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -887,10 +887,10 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter,
		bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2));
		bits &= ~(1 << VMDQ_P(0));
		bits \|= IXGBE_READ_REG(hw,
		IXGBE_VLVFB(reg_ndx * 2) + 1);
		IXGBE_VLVFB(reg_ndx * 2 + 1));
		} else {
		bits = IXGBE_READ_REG(hw,
		IXGBE_VLVFB(reg_ndx * 2) + 1);
		IXGBE_VLVFB(reg_ndx * 2 + 1));
		bits &= ~(1 << (VMDQ_P(0) - 32));
		bits \|= IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2));
		}