Commit 8e6d08e0 authored by Stefan Kristiansson's avatar Stefan Kristiansson Committed by Stafford Horne
Browse files

openrisc: initial SMP support 



This patch introduces the SMP support for the OpenRISC architecture.
The SMP architecture requires cores which have multi-core features which
have been introduced a few years back including:

 - New SPRS SPR_COREID SPR_NUMCORES
 - Shadow SPRs
 - Atomic Instructions
 - Cache Coherency
 - A wired in IPI controller

This patch adds all of the SMP specific changes to core infrastructure,
it looks big but it needs to go all together as its hard to split this
one up.

Boot loader spinning of second cpu is not supported yet, it's assumed
that Linux is booted straight after cpu reset.

The bulk of these changes are trivial changes to refactor to use per cpu
data structures throughout.  The addition of the smp.c and changes in
time.c are the changes.  Some specific notes:

MM changes
----------
The reason why this is created as an array, and not with DEFINE_PER_CPU
is that doing it this way, we'll save a load in the tlb-miss handler
(the load from __per_cpu_offset).

TLB Flush
---------
The SMP implementation of flush_tlb_* works by sending out a
function-call IPI to all the non-local cpus by using the generic
on_each_cpu() function.

Currently, all flush_tlb_* functions will result in a flush_tlb_all(),
which has always been the behaviour in the UP case.

CPU INFO
--------
This creates a per cpu cpuinfo struct and fills it out accordingly for
each activated cpu.  show_cpuinfo is also updated to reflect new version
information in later versions of the spec.

SMP API
-------
This imitates the arm64 implementation by having a smp_cross_call
callback that can be set by set_smp_cross_call to initiate an IPI and a
handle_IPI function that is expected to be called from an IPI irqchip
driver.

Signed-off-by: default avatarStefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: added cpu stop, checkpatch fixes, wrote commit message]
Signed-off-by: default avatarStafford Horne <shorne@gmail.com>
parent 9b54470a

arch/openrisc/Kconfig

+15 −2
Original line number Diff line number Diff line
@@ -21,8 +21,10 @@ config OPENRISC 
	select HAVE_UID16

	select GENERIC_ATOMIC64

	select GENERIC_CLOCKEVENTS

	select GENERIC_CLOCKEVENTS_BROADCAST

	select GENERIC_STRNCPY_FROM_USER

	select GENERIC_STRNLEN_USER

	select GENERIC_SMP_IDLE_THREAD

	select MODULES_USE_ELF_RELA

	select HAVE_DEBUG_STACKOVERFLOW

	select OR1K_PIC
@@ -107,8 +109,19 @@ config OPENRISC_HAVE_INST_DIV 
endmenu



config NR_CPUS

	int

	default "1"

	int "Maximum number of CPUs (2-32)"

	range 2 32

	depends on SMP

	default "2"



config SMP

	bool "Symmetric Multi-Processing support"

	help

	  This enables support for systems with more than one CPU. If you have

	  a system with only one CPU, say N. If you have a system with more

	  than one CPU, say Y.



	  If you don't know what to do here, say N.



source kernel/Kconfig.hz

source kernel/Kconfig.preempt

arch/openrisc/include/asm/cpuinfo.h

+5 −2
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
#ifndef __ASM_OPENRISC_CPUINFO_H

#define __ASM_OPENRISC_CPUINFO_H



struct cpuinfo {

struct cpuinfo_or1k {

	u32 clock_frequency;



	u32 icache_size;
@@ -29,8 +29,11 @@ struct cpuinfo { 
	u32 dcache_size;

	u32 dcache_block_size;

	u32 dcache_ways;



	u16 coreid;

};



extern struct cpuinfo cpuinfo;

extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];

extern void setup_cpuinfo(void);



#endif /* __ASM_OPENRISC_CPUINFO_H */

arch/openrisc/include/asm/mmu_context.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
 * registers like cr3 on the i386

 */



extern volatile pgd_t *current_pgd;   /* defined in arch/openrisc/mm/fault.c */

extern volatile pgd_t *current_pgd[]; /* defined in arch/openrisc/mm/fault.c */



static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)

{

arch/openrisc/include/asm/pgtable.h

+1 −1
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ extern void paging_init(void); 
 * 64 MB of vmalloc area is comparable to what's available on other arches.

 */



#define VMALLOC_START	(PAGE_OFFSET-0x04000000)

#define VMALLOC_START	(PAGE_OFFSET-0x04000000UL)

#define VMALLOC_END	(PAGE_OFFSET)

#define VMALLOC_VMADDR(x) ((unsigned long)(x))

arch/openrisc/include/asm/serial.h

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
 * it needs to be correct to get the early console working.

 */



#define BASE_BAUD (cpuinfo.clock_frequency/16)

#define BASE_BAUD (cpuinfo_or1k[smp_processor_id()].clock_frequency/16)



#endif /* __KERNEL__ */

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