Commit 8e466955 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 platform updates from Ingo Molnar:
 "The main changes in this cycle were:

   - Intel-SoC enhancements (Andy Shevchenko)

   - Intel CPU symbolic model definition rework (Dave Hansen)

   - ... other misc changes"

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  x86/sfi: Enable enumeration of SD devices
  x86/pci: Use MRFLD abbreviation for Merrifield
  x86/platform/intel-mid: Make vertical indentation consistent
  x86/platform/intel-mid: Mark regulators explicitly defined
  x86/platform/intel-mid: Rename mrfl.c to mrfld.c
  x86/platform/intel-mid: Enable spidev on Intel Edison boards
  x86/platform/intel-mid: Extend PWRMU to support Penwell
  x86/pci, x86/platform/intel_mid_pci: Remove duplicate power off code
  x86/platform/intel-mid: Add pinctrl for Intel Merrifield
  x86/platform/intel-mid: Enable GPIO expanders on Edison
  x86/platform/intel-mid: Add Power Management Unit driver
  x86/platform/atom/punit: Enable support for Merrifield
  x86/platform/intel_mid_pci: Rework IRQ0 workaround
  x86, thermal: Clean up and fix CPU model detection for intel_soc_dts_thermal
  x86, mmc: Use Intel family name macros for mmc driver
  x86/intel_telemetry: Use Intel family name macros for telemetry driver
  x86/acpi/lss: Use Intel family name macros for the acpi_lpss driver
  x86/cpufreq: Use Intel family name macros for the intel_pstate cpufreq driver
  x86/platform: Use new Intel model number macros
  x86/intel_idle: Use Intel family macros for intel_idle
  ...
parents 2d724ffd 05f310e2

arch/x86/include/asm/intel-mid.h

+57 −31
Original line number Diff line number Diff line
@@ -12,9 +12,17 @@ 
#define _ASM_X86_INTEL_MID_H



#include <linux/sfi.h>

#include <linux/pci.h>

#include <linux/platform_device.h>



extern int intel_mid_pci_init(void);

extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);



#define INTEL_MID_PWR_LSS_OFFSET	4

#define INTEL_MID_PWR_LSS_TYPE		(1 << 7)



extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);



extern int get_gpio_by_name(const char *name);

extern void intel_scu_device_register(struct platform_device *pdev);

extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
@@ -41,6 +49,21 @@ struct devs_id { 
	static const struct devs_id *const __intel_mid_sfi_##i##_dev __used	\

	__attribute__((__section__(".x86_intel_mid_dev.init"))) = &i



/**

* struct mid_sd_board_info - template for SD device creation

* @name:		identifies the driver

* @bus_num:		board-specific identifier for a given SD controller

* @max_clk:		the maximum frequency device supports

* @platform_data:	the particular data stored there is driver-specific

*/

struct mid_sd_board_info {

	char		name[SFI_NAME_LEN];

	int		bus_num;

	unsigned short	addr;

	u32		max_clk;

	void		*platform_data;

};



/*

 * Medfield is the follow-up of Moorestown, it combines two chip solution into

 * one. Other than that it also added always-on and constant tsc and lapic
@@ -100,8 +123,8 @@ static inline bool intel_mid_has_msic(void) 


#else /* !CONFIG_X86_INTEL_MID */



#define intel_mid_identify_cpu()    (0)

#define intel_mid_has_msic()    (0)

#define intel_mid_identify_cpu()	0

#define intel_mid_has_msic()		0



#endif /* !CONFIG_X86_INTEL_MID */
@@ -129,9 +152,12 @@ extern enum intel_mid_timer_options intel_mid_timer_options; 


/* Bus Select SoC Fuse value */

#define BSEL_SOC_FUSE_MASK		0x7

#define BSEL_SOC_FUSE_001	0x1 /* FSB 133MHz */

#define BSEL_SOC_FUSE_101	0x5 /* FSB 100MHz */

#define BSEL_SOC_FUSE_111	0x7 /* FSB 83MHz */

/* FSB 133MHz */

#define BSEL_SOC_FUSE_001		0x1

/* FSB 100MHz */

#define BSEL_SOC_FUSE_101		0x5

/* FSB 83MHz */

#define BSEL_SOC_FUSE_111		0x7



#define SFI_MTMR_MAX_NUM		8

#define SFI_MRTC_MAX			8
@@ -140,12 +166,12 @@ extern void intel_scu_devices_create(void); 
extern void intel_scu_devices_destroy(void);



/* VRTC timer */

#define MRST_VRTC_MAP_SZ	(1024)

/*#define MRST_VRTC_PGOFFSET	(0xc00) */

#define MRST_VRTC_MAP_SZ		1024

/* #define MRST_VRTC_PGOFFSET		0xc00 */



extern void intel_mid_rtc_init(void);



/* the offset for the mapping of global gpio pin to irq */

/* The offset for the mapping of global gpio pin to irq */

#define INTEL_MID_IRQ_OFFSET		0x100



#endif /* _ASM_X86_INTEL_MID_H */

arch/x86/include/asm/topology.h

+1 −11
Original line number Diff line number Diff line
@@ -25,16 +25,6 @@ 
#ifndef _ASM_X86_TOPOLOGY_H

#define _ASM_X86_TOPOLOGY_H



#ifdef CONFIG_X86_32

# ifdef CONFIG_SMP

#  define ENABLE_TOPO_DEFINES

# endif

#else

# ifdef CONFIG_SMP

#  define ENABLE_TOPO_DEFINES

# endif

#endif



/*

 * to preserve the visibility of NUMA_NO_NODE definition,

 * moved to there from here.  May be used independent of
@@ -123,7 +113,7 @@ extern const struct cpumask *cpu_coregroup_mask(int cpu); 
#define topology_physical_package_id(cpu)	(cpu_data(cpu).phys_proc_id)

#define topology_core_id(cpu)			(cpu_data(cpu).cpu_core_id)



#ifdef ENABLE_TOPO_DEFINES

#ifdef CONFIG_SMP

#define topology_core_cpumask(cpu)		(per_cpu(cpu_core_map, cpu))

#define topology_sibling_cpumask(cpu)		(per_cpu(cpu_sibling_map, cpu))

arch/x86/kernel/cpu/intel.c

+3 −4
Original line number Diff line number Diff line
@@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c) 
	}



	/*

	 * P4 Xeon errata 037 workaround.

	 * P4 Xeon erratum 037 workaround.

	 * Hardware prefetcher may cause stale data to be loaded into the cache.

	 */

	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {

		if (msr_set_bit(MSR_IA32_MISC_ENABLE,

				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)

		    > 0) {

				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {

			pr_info("CPU: C0 stepping P4 Xeon detected.\n");

			pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");

			pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");

		}

	}

arch/x86/pci/intel_mid_pci.c

+42 −9
Original line number Diff line number Diff line
@@ -36,7 +36,8 @@ 
#define PCIE_CAP_OFFSET	0x100



/* Quirks for the listed devices */

#define PCI_DEVICE_ID_INTEL_MRFL_MMC	0x1190

#define PCI_DEVICE_ID_INTEL_MRFLD_MMC	0x1190

#define PCI_DEVICE_ID_INTEL_MRFLD_HSU	0x1191



/* Fixed BAR fields */

#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00	/* Fixed BAR (TBD) */
@@ -224,14 +225,21 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) 


		/* Special treatment for IRQ0 */

		if (dev->irq == 0) {

			/*

			 * Skip HS UART common registers device since it has

			 * IRQ0 assigned and not used by the kernel.

			 */

			if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)

				return -EBUSY;

			/*

			 * TNG has IRQ0 assigned to eMMC controller. But there

			 * are also other devices with bogus PCI configuration

			 * that have IRQ0 assigned. This check ensures that

			 * eMMC gets it.

			 * eMMC gets it. The rest of devices still could be

			 * enabled without interrupt line being allocated.

			 */

			if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)

				return -EBUSY;

			if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)

				return 0;

		}

		break;

	default:
@@ -308,14 +316,39 @@ static void pci_d3delay_fixup(struct pci_dev *dev) 
}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);



static void mrst_power_off_unused_dev(struct pci_dev *dev)

static void mid_power_off_one_device(struct pci_dev *dev)

{

	u16 pmcsr;



	/*

	 * Update current state first, otherwise PCI core enforces PCI_D0 in

	 * pci_set_power_state() for devices which status was PCI_UNKNOWN.

	 */

	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);

	dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);



	pci_set_power_state(dev, PCI_D3hot);

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);



static void mid_power_off_devices(struct pci_dev *dev)

{

	int id;



	if (!pci_soc_mode)

		return;



	id = intel_mid_pwr_get_lss_id(dev);

	if (id < 0)

		return;



	/*

	 * This sets only PMCSR bits. The actual power off will happen in

	 * arch/x86/platform/intel-mid/pwr.c.

	 */

	mid_power_off_one_device(dev);

}



DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices);



/*

 * Langwell devices reside at fixed offsets, don't try to move them.

arch/x86/platform/atom/punit_atom_debug.c

+16 −4
Original line number Diff line number Diff line
@@ -23,10 +23,9 @@ 
#include <linux/seq_file.h>

#include <linux/io.h>

#include <asm/cpu_device_id.h>

#include <asm/intel-family.h>

#include <asm/iosf_mbi.h>



/* Power gate status reg */

#define PWRGT_STATUS		0x61

/* Subsystem config/status Video processor */

#define VED_SS_PM0		0x32

/* Subsystem config/status ISP (Image Signal Processor) */
@@ -35,12 +34,16 @@ 
#define MIO_SS_PM		0x3B

/* Shift bits for getting status for video, isp and i/o */

#define SSS_SHIFT		24



/* Power gate status reg */

#define PWRGT_STATUS		0x61

/* Shift bits for getting status for graphics rendering */

#define RENDER_POS		0

/* Shift bits for getting status for media control */

#define MEDIA_POS		2

/* Shift bits for getting status for Valley View/Baytrail display */

#define VLV_DISPLAY_POS		6



/* Subsystem config/status display for Cherry Trail SOC */

#define CHT_DSP_SSS		0x36

/* Shift bits for getting status for display */
@@ -52,6 +55,14 @@ struct punit_device { 
	int sss_pos;

};



static const struct punit_device punit_device_tng[] = {

	{ "DISPLAY",	CHT_DSP_SSS,	SSS_SHIFT },

	{ "VED",	VED_SS_PM0,	SSS_SHIFT },

	{ "ISP",	ISP_SS_PM0,	SSS_SHIFT },

	{ "MIO",	MIO_SS_PM,	SSS_SHIFT },

	{ NULL }

};



static const struct punit_device punit_device_byt[] = {

	{ "GFX RENDER",	PWRGT_STATUS,	RENDER_POS },

	{ "GFX MEDIA",	PWRGT_STATUS,	MEDIA_POS },
@@ -143,8 +154,9 @@ static void punit_dbgfs_unregister(void) 
	  (kernel_ulong_t)&drv_data }



static const struct x86_cpu_id intel_punit_cpu_ids[] = {

	ICPU(55, punit_device_byt), /* Valleyview, Bay Trail */

	ICPU(76, punit_device_cht), /* Braswell, Cherry Trail */

	ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt),

	ICPU(INTEL_FAM6_ATOM_MERRIFIELD1, punit_device_tng),

	ICPU(INTEL_FAM6_ATOM_AIRMONT,	  punit_device_cht),

	{}

};

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