drm/nouveau/gr/gf100-: store fecs/gpccs falcon pointers in substructures (8e44b987) · Commits · 戴 / test

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+20 −16

Original line number	Diff line number	Diff line
		@@ -1645,12 +1645,12 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
		if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
		secboot_mask \|= BIT(NVKM_SECBOOT_FALCON_FECS);
		else
		gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d);
		gf100_gr_init_fw(gr->fecs.falcon, &gr->fuc409c, &gr->fuc409d);

		if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
		secboot_mask \|= BIT(NVKM_SECBOOT_FALCON_GPCCS);
		else
		gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad);
		gf100_gr_init_fw(gr->gpccs.falcon, &gr->fuc41ac, &gr->fuc41ad);

		if (secboot_mask != 0) {
		int ret = nvkm_secboot_reset(sb, secboot_mask);
		@@ -1665,8 +1665,8 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
		nvkm_wr32(device, 0x41a10c, 0x00000000);
		nvkm_wr32(device, 0x40910c, 0x00000000);

		nvkm_falcon_start(gr->gpccs);
		nvkm_falcon_start(gr->fecs);
		nvkm_falcon_start(gr->gpccs.falcon);
		nvkm_falcon_start(gr->fecs.falcon);

		if (nvkm_msec(device, 2000,
		if (nvkm_rd32(device, 0x409800) & 0x00000001)
		@@ -1728,15 +1728,19 @@ gf100_gr_init_ctxctl_int(struct gf100_gr *gr)

		/* load HUB microcode */
		nvkm_mc_unk260(device, 0);
		nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0,
		nvkm_falcon_load_dmem(gr->fecs.falcon,
		gr->func->fecs.ucode->data.data, 0x0,
		gr->func->fecs.ucode->data.size, 0);
		nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0,
		nvkm_falcon_load_imem(gr->fecs.falcon,
		gr->func->fecs.ucode->code.data, 0x0,
		gr->func->fecs.ucode->code.size, 0, 0, false);

		/* load GPC microcode */
		nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0,
		nvkm_falcon_load_dmem(gr->gpccs.falcon,
		gr->func->gpccs.ucode->data.data, 0x0,
		gr->func->gpccs.ucode->data.size, 0);
		nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0,
		nvkm_falcon_load_imem(gr->gpccs.falcon,
		gr->func->gpccs.ucode->code.data, 0x0,
		gr->func->gpccs.ucode->code.size, 0, 0, false);
		nvkm_mc_unk260(device, 1);

		@@ -1883,11 +1887,11 @@ gf100_gr_oneinit(struct nvkm_gr *base)
		int i, j;
		int ret;

		ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs);
		ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs.falcon);
		if (ret)
		return ret;

		ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs);
		ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs.falcon);
		if (ret)
		return ret;

		@@ -1930,11 +1934,11 @@ gf100_gr_init_(struct nvkm_gr *base)

		nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);

		ret = nvkm_falcon_get(gr->fecs, subdev);
		ret = nvkm_falcon_get(gr->fecs.falcon, subdev);
		if (ret)
		return ret;

		ret = nvkm_falcon_get(gr->gpccs, subdev);
		ret = nvkm_falcon_get(gr->gpccs.falcon, subdev);
		if (ret)
		return ret;

		@@ -1946,8 +1950,8 @@ gf100_gr_fini_(struct nvkm_gr *base, bool suspend)
		{
		struct gf100_gr *gr = gf100_gr(base);
		struct nvkm_subdev *subdev = &gr->base.engine.subdev;
		nvkm_falcon_put(gr->gpccs, subdev);
		nvkm_falcon_put(gr->fecs, subdev);
		nvkm_falcon_put(gr->gpccs.falcon, subdev);
		nvkm_falcon_put(gr->fecs.falcon, subdev);
		return 0;
		}

		@@ -1973,8 +1977,8 @@ gf100_gr_dtor(struct nvkm_gr *base)
		gr->func->dtor(gr);
		kfree(gr->data);

		nvkm_falcon_del(&gr->gpccs);
		nvkm_falcon_del(&gr->fecs);
		nvkm_falcon_del(&gr->gpccs.falcon);
		nvkm_falcon_del(&gr->fecs.falcon);

		gf100_gr_dtor_fw(&gr->fuc409c);
		gf100_gr_dtor_fw(&gr->fuc409d);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

+8 −2

Original line number	Diff line number	Diff line
		@@ -82,8 +82,14 @@ struct gf100_gr {
		const struct gf100_gr_func *func;
		struct nvkm_gr base;

		struct nvkm_falcon *fecs;
		struct nvkm_falcon *gpccs;
		struct {
		struct nvkm_falcon *falcon;
		} fecs;

		struct {
		struct nvkm_falcon *falcon;
		} gpccs;

		struct gf100_gr_fuc fuc409c;
		struct gf100_gr_fuc fuc409d;
		struct gf100_gr_fuc fuc41ac;

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