Commit 8e43a905 authored Feb 15, 2012 by Rabin Vincent Committed by Russell King Feb 15, 2012

ARM: 7325/1: fix v7 boot with lockdep enabled



Bootup with lockdep enabled has been broken on v7 since b46c0f74
("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").

This is because v7_setup (which is called very early during boot) calls
v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
ends up attempting to call into lockdep C code (trace_hardirqs_off())
when we are in no position to execute it (no stack, MMU off).

Fix this by using a notrace variant of save_and_disable_irqs.  The code
already uses the notrace variant of restore_irqs.

Reviewed-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 6e2e340b

arch/arm/include/asm/assembler.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -137,6 +137,11 @@
		disable_irq
		.endm

		.macro save_and_disable_irqs_notrace, oldcpsr
		mrs \oldcpsr, cpsr
		disable_irq_notrace
		.endm

		/*
		* Restore interrupt state previously stored in a register. We don't
		* guarantee that this will preserve the flags.

arch/arm/mm/cache-v7.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -55,7 +55,7 @@ loop1:
		cmp r1, #2 @ see what cache we have at this level
		blt skip @ skip if no cache, or just i-cache
		#ifdef CONFIG_PREEMPT
		save_and_disable_irqs r9 @ make cssr&csidr read atomic
		save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
		#endif
		mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
		isb @ isb to sych the new cssr&csidr

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