perf/x86/intel/pt: Factor out pt_config_start() (8e105a1f) · Commits · 戴 / test

PT trace is now enabled at the bottom of the event configuration function that takes care of all configuration bits related to a given event, including the address filter update. This is only needed where the event configuration changes, that is, in ->add()/->start(). In the interrupt path we can use a lighter version that keeps the configuration intact, since it hasn't changed, and only flips the enable bit. Signed-off-by:

Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by:

Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: David Ahern <dsahern@gmail.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: adrian.hunter@intel.com Cc: mathieu.poirier@linaro.org Link: https://lkml.kernel.org/r/20191025140835.53665-3-alexander.shishkin@linux.intel.com Signed-off-by:

Ingo Molnar <mingo@kernel.org>

arch/x86/events/intel/pt.c

+16 −6

Original line number	Diff line number	Diff line
		@@ -397,6 +397,20 @@ static bool pt_event_valid(struct perf_event *event)
		* These all are cpu affine and operate on a local PT
		*/

		static void pt_config_start(struct perf_event *event)
		{
		struct pt *pt = this_cpu_ptr(&pt_ctx);
		u64 ctl = event->hw.config;

		ctl \|= RTIT_CTL_TRACEEN;
		if (READ_ONCE(pt->vmx_on))
		perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
		else
		wrmsrl(MSR_IA32_RTIT_CTL, ctl);

		WRITE_ONCE(event->hw.config, ctl);
		}

		/* Address ranges and their corresponding msr configuration registers */
		static const struct pt_address_range {
		unsigned long msr_a;
		@@ -468,7 +482,6 @@ static u64 pt_config_filters(struct perf_event *event)

		static void pt_config(struct perf_event *event)
		{
		struct pt *pt = this_cpu_ptr(&pt_ctx);
		u64 reg;

		/* First round: clear STATUS, in particular the PSB byte counter. */
		@@ -501,10 +514,7 @@ static void pt_config(struct perf_event *event)
		reg \|= (event->attr.config & PT_CONFIG_MASK);

		event->hw.config = reg;
		if (READ_ONCE(pt->vmx_on))
		perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
		else
		wrmsrl(MSR_IA32_RTIT_CTL, reg);
		pt_config_start(event);
		}

		static void pt_config_stop(struct perf_event *event)
		@@ -1381,7 +1391,7 @@ void intel_pt_interrupt(void)

		pt_config_buffer(topa_to_page(buf->cur)->table, buf->cur_idx,
		buf->output_off);
		pt_config(event);
		pt_config_start(event);
		}
		}

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