Commit 8e02676f authored Aug 31, 2016 by Torgue Alexandre Committed by Russell King Sep 06, 2016

ARM: 8610/1: V7M: Add dsb before jumping in handler mode



According to ARM AN321 (section 4.12):

"If the vector table is in writable memory such as SRAM, either relocated
by VTOR or a device dependent memory remapping mechanism, then
architecturally a memory barrier instruction is required after the vector
table entry is updated, and if the exception is to be activated
immediately"

Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 6a8146f4

arch/arm/mm/proc-v7m.S

+1 −0

Original line number	Diff line number	Diff line
		@@ -132,6 +132,7 @@ __v7m_setup_cont:
		badr r1, 1f
		ldr r5, [r12, #11 * 4] @ read the SVC vector entry
		str r1, [r12, #11 * 4] @ write the temporary SVC vector entry
		dsb
		mov r6, lr @ save LR
		ldr sp, =init_thread_union + THREAD_START_SP
		cpsie i

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