Commit 8de9930a authored by Borislav Petkov's avatar Borislav Petkov
Browse files

Revert "EDAC/amd64: Support more than two controllers for chip select handling" 



This reverts commit 0a227af5.

Unfortunately, this commit caused wrong detection of chip select sizes
on some F17h client machines:

  --- 00-rc6+     2019-02-14 14:28:03.126622904 +0100
  +++ 01-rc4+     2019-04-14 21:06:16.060614790 +0200
   EDAC amd64: MC: 0:     0MB 1:     0MB
  -EDAC amd64: MC: 2: 16383MB 3: 16383MB
  +EDAC amd64: MC: 2:     0MB 3: 2097151MB
   EDAC amd64: MC: 4:     0MB 5:     0MB
   EDAC amd64: MC: 6:     0MB 7:     0MB
   EDAC MC: UMC1 chip selects:
   EDAC amd64: MC: 0:     0MB 1:     0MB
  -EDAC amd64: MC: 2: 16383MB 3: 16383MB
  +EDAC amd64: MC: 2:     0MB 3: 2097151MB
   EDAC amd64: MC: 4:     0MB 5:     0MB
   EDAC amd64: MC: 6:     0MB 7:     0M

Revert it for now until it has been solved properly.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Yazen Ghannam <yazen.ghannam@amd.com>
parent 74676a8e

drivers/edac/amd64_edac.c

+54 −59
Original line number Diff line number Diff line
@@ -941,64 +941,48 @@ static void prep_chip_selects(struct amd64_pvt *pvt) 
	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {

		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;

		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;

	} else if (pvt->fam >= 0x17) {

		int umc;



		for_each_umc(umc) {

			pvt->csels[umc].b_cnt = 8;

			pvt->csels[umc].m_cnt = 4;

		}



	} else {

		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;

		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;

	}

}



static void read_umc_base_mask(struct amd64_pvt *pvt)

{

	int cs, umc;



	for_each_umc(umc) {

		u32 umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;

		u32 umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;



		for_each_chip_select(cs, 0, pvt) {

			u32 *base = &pvt->csels[umc].csbases[cs];

			u32 *mask = &pvt->csels[umc].csmasks[cs];



			u32 base_reg = umc_base_reg + (cs * 4);

			u32 mask_reg = umc_mask_reg + ((cs >> 1) * 4);



			if (!amd_smn_read(pvt->mc_node_id, base_reg, base))

				edac_dbg(0, "  DCSB%d[%d]=0x%08x reg: 0x%x\n",

					 umc, cs, *base, base_reg);



			if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask))

				edac_dbg(0, "    DCSM%d[%d]=0x%08x reg: 0x%x\n",

					 umc, cs, *mask, mask_reg);

		}

	}

}



/*

 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers

 */

static void read_dct_base_mask(struct amd64_pvt *pvt)

{

	int cs;

	int base_reg0, base_reg1, mask_reg0, mask_reg1, cs;



	prep_chip_selects(pvt);



	if (pvt->umc)

		return read_umc_base_mask(pvt);

	if (pvt->umc) {

		base_reg0 = get_umc_base(0) + UMCCH_BASE_ADDR;

		base_reg1 = get_umc_base(1) + UMCCH_BASE_ADDR;

		mask_reg0 = get_umc_base(0) + UMCCH_ADDR_MASK;

		mask_reg1 = get_umc_base(1) + UMCCH_ADDR_MASK;

	} else {

		base_reg0 = DCSB0;

		base_reg1 = DCSB1;

		mask_reg0 = DCSM0;

		mask_reg1 = DCSM1;

	}



	for_each_chip_select(cs, 0, pvt) {

		int reg0   = DCSB0 + (cs * 4);

		int reg1   = DCSB1 + (cs * 4);

		int reg0   = base_reg0 + (cs * 4);

		int reg1   = base_reg1 + (cs * 4);

		u32 *base0 = &pvt->csels[0].csbases[cs];

		u32 *base1 = &pvt->csels[1].csbases[cs];



		if (pvt->umc) {

			if (!amd_smn_read(pvt->mc_node_id, reg0, base0))

				edac_dbg(0, "  DCSB0[%d]=0x%08x reg: 0x%x\n",

					 cs, *base0, reg0);



			if (!amd_smn_read(pvt->mc_node_id, reg1, base1))

				edac_dbg(0, "  DCSB1[%d]=0x%08x reg: 0x%x\n",

					 cs, *base1, reg1);

		} else {

			if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))

				edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",

					 cs, *base0, reg0);
@@ -1011,13 +995,23 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) 
					 cs, *base1, (pvt->fam == 0x10) ? reg1

								: reg0);

		}

	}



	for_each_chip_select_mask(cs, 0, pvt) {

		int reg0   = DCSM0 + (cs * 4);

		int reg1   = DCSM1 + (cs * 4);

		int reg0   = mask_reg0 + (cs * 4);

		int reg1   = mask_reg1 + (cs * 4);

		u32 *mask0 = &pvt->csels[0].csmasks[cs];

		u32 *mask1 = &pvt->csels[1].csmasks[cs];



		if (pvt->umc) {

			if (!amd_smn_read(pvt->mc_node_id, reg0, mask0))

				edac_dbg(0, "    DCSM0[%d]=0x%08x reg: 0x%x\n",

					 cs, *mask0, reg0);



			if (!amd_smn_read(pvt->mc_node_id, reg1, mask1))

				edac_dbg(0, "    DCSM1[%d]=0x%08x reg: 0x%x\n",

					 cs, *mask1, reg1);

		} else {

			if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))

				edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",

					 cs, *mask0, reg0);
@@ -1031,6 +1025,7 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) 
								: reg0);

		}

	}

}



static void determine_memory_type(struct amd64_pvt *pvt)

{

drivers/edac/amd64_edac.h

+2 −3
Original line number Diff line number Diff line
@@ -96,7 +96,6 @@ 
/* Hardware limit on ChipSelect rows per MC and processors per system */

#define NUM_CHIPSELECTS			8

#define DRAM_RANGES			8

#define NUM_CONTROLLERS			8



#define ON true

#define OFF false
@@ -352,8 +351,8 @@ struct amd64_pvt { 
	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */

	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */



	/* one for each DCT/UMC */

	struct chip_select csels[NUM_CONTROLLERS];

	/* one for each DCT */

	struct chip_select csels[2];



	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */

	struct dram_range ranges[DRAM_RANGES];

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