Unverified Commit 8dd71698 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Mark Brown
Browse files

spi: rspi: Clean up Bit Rate Division Setting handling 



Add a macro for configuring the Bit Rate Division Setting field in
Command Registers, instead of open-coding the same operation using a
hardcoded shift.
Rename "div" to "brdv", as it is not a plain divider value, but controls
a power-of-two divider.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200819125904.20938-3-geert+renesas@glider.be


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7ffe363b

drivers/spi/spi-rspi.c

+5 −4
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ 
#define SPCMD_SPRW		0x0010	/* SPI Read/Write Access (Dual/Quad) */

#define SPCMD_SSLA(i)		((i) << 4)	/* SSL Assert Signal Setting */

#define SPCMD_BRDV_MASK		0x000c	/* Bit Rate Division Setting */

#define SPCMD_BRDV(brdv)	((brdv) << 2)

#define SPCMD_CPOL		0x0002	/* Clock Polarity Setting */

#define SPCMD_CPHA		0x0001	/* Clock Phase Setting */
@@ -290,24 +291,24 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 
static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)

{

	int spbr;

	int div = 0;

	int brdv = 0;

	unsigned long clksrc;



	/* Sets output mode, MOSI signal, and (optionally) loopback */

	rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);



	clksrc = clk_get_rate(rspi->clk);

	while (div < 3) {

	while (brdv < 3) {

		if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */

			break;

		div++;

		brdv++;

		clksrc /= 2;

	}



	/* Sets transfer bit rate */

	spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;

	rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);

	rspi->spcmd |= div << 2;

	rspi->spcmd |= SPCMD_BRDV(brdv);



	/* Disable dummy transmission, set byte access */

	rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);

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