Commit 8dcfdfb4 authored Jun 10, 2019 by Lionel Landwerlin

drm/i915/perf: fix ICL perf register offsets

We got the wrong offsets (could they have changed?). New values were
computed off an error state by looking up the register offset in the
context image as written by the HW.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1de401c0 ("drm/i915/perf: enable perf support on ICL")
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190610081914.25428-1-lionel.g.landwerlin@intel.com

parent f9a39387

drivers/gpu/drm/i915/i915_perf.c

+7 −3

Original line number	Diff line number	Diff line
		@@ -3479,9 +3479,13 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
		dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
		dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;

		if (IS_GEN(dev_priv, 10)) {
		dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
		dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;

		} else {
		dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124;
		dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e;
		}
		dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
		}
		}