Commit 8d9c5f34 authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller
Browse files

bnx2x: New FW 



This is the FW blob and the relevant definitions without any logic. It
also contains the minimal mandatory code changes to work with this FW
but it does not contain enabling of the new features that this FW
provides.

This FW is needed for:
- More efficient multi-queue
- per queue statistics
- Big-endian issue with MSI
- Improved pause response

Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 33af6bcc

drivers/net/bnx2x.h

+1 −1
Original line number Diff line number Diff line
@@ -1125,7 +1125,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 
		 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \

		 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \

		 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \

		 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)

		 TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE)



#define MULTI_MASK			0x7f

drivers/net/bnx2x_fw_defs.h

+36 −34
Original line number Diff line number Diff line
@@ -50,8 +50,10 @@ 
#define TSTORM_ASSERT_LIST_OFFSET(idx) \

	(IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))

#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \

	(IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \

	: (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))

	(IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \

	: (0x9c0 + (port * 0x130) + (client_id * 0x10)))

#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \

	(IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff)

#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \

	(IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \

	((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -81,43 +83,43 @@ 
	(function * 0x38)))

#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \

	(IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \

	0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))

#define TSTORM_RX_PRODS_OFFSET(port, client_id) \

	(IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \

	: (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))

	0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50)))

#define TSTORM_STATS_FLAGS_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \

	(function * 0x8)))

#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20)

#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20)

#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)

#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)

#define USTORM_ASSERT_LIST_INDEX_OFFSET \

	(IS_E1H_OFFSET ? 0x8000 : 0x1000)

	(IS_E1H_OFFSET ? 0x8960 : 0x1000)

#define USTORM_ASSERT_LIST_OFFSET(idx) \

	(IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))

	(IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))

#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \

	(IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \

	(0x5450 + (port * 0x1c8) + (clientId * 0x18)))

	(IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \

	(0x5330 + (port * 0x260) + (clientId * 0x20)))

#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \

	(IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \

	((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \

	0x28) + (index * 0x4)))

	(IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \

	((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \

	0x40) + (index * 0x4)))

#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \

	((function&1) * 0x100)) : (0x1900 + (function * 0x40)))

#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))

	(IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \

	((function&1) * 0x100)) : (0x1908 + (function * 0x40)))

#define USTORM_FUNCTION_MODE_OFFSET \

	(IS_E1H_OFFSET ? 0x2448 : 0xffffffff)

#define USTORM_HC_BTR_OFFSET(port) \

	(IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))

	(IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))

#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \

	(IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \

	(0x5448 + (port * 0x1c8) + (clientId * 0x18)))

	(IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \

	(0x5328 + (port * 0x260) + (clientId * 0x20)))

#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \

	(IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \

	(function * 0x8)))

#define USTORM_RX_PRODS_OFFSET(port, client_id) \

	(IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \

	: (0x5318 + (port * 0x260) + (client_id * 0x20)))

#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \

	(IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \

	(index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
@@ -137,7 +139,7 @@ 
#define XSTORM_ASSERT_LIST_OFFSET(idx) \

	(IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))

#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \

	(IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))

	(IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50)))

#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \

	(IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \

	((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -149,23 +151,23 @@ 
	(IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \

	((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))

#define XSTORM_E1HOV_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)

	(IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff)

#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \

	(function * 0x8)))

#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \

	(function * 0x70)))

	(IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \

	(function * 0x90)))

#define XSTORM_FUNCTION_MODE_OFFSET \

	(IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)

	(IS_E1H_OFFSET ? 0x2c20 : 0xffffffff)

#define XSTORM_HC_BTR_OFFSET(port) \

	(IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))

#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \

	(IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \

	0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))

#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \

	(function * 0x70)))

	(IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \

	(function * 0x90)))

#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \

	(IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \

	(function * 0x10)))
@@ -278,9 +280,6 @@ 
#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)

#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)

#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)

#define ISCSI_STATE \

	(ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)

#define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)



/* microcode fixed page page size 4K (chains and ring segments) */

#define MC_PAGE_SIZE (4096)
@@ -289,7 +288,7 @@ 
/* Host coalescing constants */



/* index numbers */

#define HC_USTORM_DEF_SB_NUM_INDICES 4

#define HC_USTORM_DEF_SB_NUM_INDICES 8

#define HC_CSTORM_DEF_SB_NUM_INDICES 8

#define HC_XSTORM_DEF_SB_NUM_INDICES 4

#define HC_TSTORM_DEF_SB_NUM_INDICES 4
@@ -386,9 +385,12 @@ 
#define FW_LOG_LIST_SIZE (50)



#define NUM_OF_PROTOCOLS 4

#define MAX_COS_NUMBER 16

#define NUM_OF_SAFC_BITS 16

#define MAX_COS_NUMBER 4

#define MAX_T_STAT_COUNTER_ID 18

#define MAX_X_STAT_COUNTER_ID 18

#define MAX_U_STAT_COUNTER_ID 18





#define UNKNOWN_ADDRESS 0

#define UNICAST_ADDRESS 1

drivers/net/bnx2x_hsi.h

+91 −83
Original line number Diff line number Diff line
@@ -1212,8 +1212,9 @@ struct host_func_stats { 




#define BCM_5710_FW_MAJOR_VERSION			4

#define BCM_5710_FW_MINOR_VERSION			5

#define BCM_5710_FW_REVISION_VERSION			1

#define BCM_5710_FW_MINOR_VERSION			8

#define BCM_5710_FW_REVISION_VERSION			53

#define BCM_5710_FW_ENGINEERING_VERSION 		0

#define BCM_5710_FW_COMPILE_FLAGS			1
@@ -1465,9 +1466,11 @@ struct ustorm_eth_st_context_config { 
#endif

#if defined(__BIG_ENDIAN)

	u16 bd_buff_size;

	u16 mc_alignment_size;

	u8 statistics_counter_id;

	u8 mc_alignment_log_size;

#elif defined(__LITTLE_ENDIAN)

	u16 mc_alignment_size;

	u8 mc_alignment_log_size;

	u8 statistics_counter_id;

	u16 bd_buff_size;

#endif

#if defined(__BIG_ENDIAN)
@@ -1479,13 +1482,7 @@ struct ustorm_eth_st_context_config { 
	u8 __local_bd_prod;

	u8 __local_sge_prod;

#endif

#if defined(__BIG_ENDIAN)

	u16 __bd_cons;

	u16 __sge_cons;

#elif defined(__LITTLE_ENDIAN)

	u16 __sge_cons;

	u16 __bd_cons;

#endif

	u32 reserved;

	u32 bd_page_base_lo;

	u32 bd_page_base_hi;

	u32 sge_page_base_lo;
@@ -2162,9 +2159,9 @@ struct host_status_block { 
 * The data for RSS setup ramrod

 */

struct eth_client_setup_ramrod_data {

	u32 client_id_5b;

	u8 is_rdma_1b;

	u8 reserved0;

	u32 client_id;

	u8 is_rdma;

	u8 is_fcoe;

	u16 reserved1;

};
@@ -2225,7 +2222,7 @@ struct eth_fast_path_rx_cqe { 
 * The data for RSS setup ramrod

 */

struct eth_halt_ramrod_data {

	u32 client_id_5b;

	u32 client_id;

	u32 reserved0;

};
@@ -2236,11 +2233,11 @@ struct eth_halt_ramrod_data { 
struct eth_query_ramrod_data {

#if defined(__BIG_ENDIAN)

	u8 reserved0;

	u8 collect_port_1b;

	u8 collect_port;

	u16 drv_counter;

#elif defined(__LITTLE_ENDIAN)

	u16 drv_counter;

	u8 collect_port_1b;

	u8 collect_port;

	u8 reserved0;

#endif

	u32 ctr_id_vector;
@@ -2282,7 +2279,7 @@ struct common_ramrod_eth_rx_cqe { 
#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0

#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)

#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1

	u8 conn_type_3b;

	u8 conn_type;

	u16 reserved1;

	u32 conn_and_cmd_data;

#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
@@ -2377,14 +2374,16 @@ struct tstorm_eth_function_common_config { 
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10

#elif defined(__LITTLE_ENDIAN)

	u16 config_flags;

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
@@ -2395,14 +2394,16 @@ struct tstorm_eth_function_common_config { 
#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)

#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)

#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10

	u8 rss_result_mask;

	u8 leading_client_id;

#endif
@@ -2422,7 +2423,7 @@ struct eth_update_ramrod_data { 
 * MAC filtering configuration command header

 */

struct mac_configuration_hdr {

	u8 length_6b;

	u8 length;

	u8 offset;

	u16 client_id;

	u32 reserved1;
@@ -2544,24 +2545,28 @@ struct tstorm_eth_client_config { 
#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4

	u16 config_flags;

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0

#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)

#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4

#elif defined(__LITTLE_ENDIAN)

	u16 config_flags;

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)

#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0

#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)

#define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)

#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)

#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)

#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4

	u16 drop_flags;

#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)

#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
@@ -2593,10 +2598,27 @@ struct tstorm_eth_mac_filter_config { 
};





/*

 * common flag to indicate existance of TPA.

 */

struct tstorm_eth_tpa_exist {

#if defined(__BIG_ENDIAN)

	u16 reserved1;

	u8 reserved0;

	u8 tpa_exist;

#elif defined(__LITTLE_ENDIAN)

	u8 tpa_exist;

	u8 reserved0;

	u16 reserved1;

#endif

	u32 reserved2;

};





/*

 * Three RX producers for ETH

 */

struct tstorm_eth_rx_producers {

struct ustorm_eth_rx_producers {

#if defined(__BIG_ENDIAN)

	u16 bd_prod;

	u16 cqe_prod;
@@ -2614,23 +2636,6 @@ struct tstorm_eth_rx_producers { 
};





/*

 * common flag to indicate existence of TPA.

 */

struct tstorm_eth_tpa_exist {

#if defined(__BIG_ENDIAN)

	u16 reserved1;

	u8 reserved0;

	u8 tpa_exist;

#elif defined(__LITTLE_ENDIAN)

	u8 tpa_exist;

	u8 reserved0;

	u16 reserved1;

#endif

	u32 reserved2;

};





/*

 * per-port SAFC demo variables

 */
@@ -2674,15 +2679,15 @@ struct fairness_vars_per_port { 
 */

struct safc_struct_per_port {

#if defined(__BIG_ENDIAN)

	u16 __reserved0;

	u8 cur_cos_types;

	u16 __reserved1;

	u8 __reserved0;

	u8 safc_timeout_usec;

#elif defined(__LITTLE_ENDIAN)

	u8 safc_timeout_usec;

	u8 cur_cos_types;

	u16 __reserved0;

	u8 __reserved0;

	u16 __reserved1;

#endif

	u8 cos_to_protocol[MAX_COS_NUMBER];

	u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];

};
@@ -2788,13 +2793,15 @@ struct fairness_vars_per_vn { 
 */

struct fw_version {

#if defined(__BIG_ENDIAN)

	u16 patch;

	u8 primary;

	u8 client;

	u8 engineering;

	u8 revision;

	u8 minor;

	u8 major;

#elif defined(__LITTLE_ENDIAN)

	u8 client;

	u8 primary;

	u16 patch;

	u8 major;

	u8 minor;

	u8 revision;

	u8 engineering;

#endif

	u32 flags;

#define FW_VERSION_OPTIMIZED (0x1<<0)
@@ -2812,9 +2819,10 @@ struct fw_version { 
 * FW version stored in first line of pram

 */

struct pram_fw_version {

	u8 client;

	u8 primary;

	u16 patch;

	u8 major;

	u8 minor;

	u8 revision;

	u8 engineering;

	u8 flags;

#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)

#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0

drivers/net/bnx2x_init_values.h

+14055 −12472

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/bnx2x_main.c

+46 −43
Original line number Diff line number Diff line
@@ -1377,7 +1377,7 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 
					u16 bd_prod, u16 rx_comp_prod,

					u16 rx_sge_prod)

{

	struct tstorm_eth_rx_producers rx_prods = {0};

	struct ustorm_eth_rx_producers rx_prods = {0};

	int i;



	/* Update producers */
@@ -1395,9 +1395,9 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 
	 */

	wmb();



	for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++)

		REG_WR(bp, BAR_TSTRORM_INTMEM +

		       TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,

	for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)

		REG_WR(bp, BAR_USTRORM_INTMEM +

		       USTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,

		       ((u32 *)&rx_prods)[i]);



	mmiowb(); /* keep prod updates ordered */
@@ -2915,7 +2915,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 
		return IRQ_HANDLED;

	}



	bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);

	bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);



#ifdef BNX2X_STOP_ON_ERROR

	if (unlikely(bp->panic))
@@ -3043,7 +3043,7 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp) 
		int rc;



		ramrod_data.drv_counter = bp->stats_counter++;

		ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0;

		ramrod_data.collect_port = bp->port.pmf ? 1 : 0;

		ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));



		rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
@@ -4240,10 +4240,6 @@ static void bnx2x_update_coalesce(struct bnx2x *bp) 
			 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,

						     U_SB_ETH_RX_CQ_INDEX),

			 bp->rx_ticks ? 0 : 1);

		REG_WR16(bp, BAR_USTRORM_INTMEM +

			 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,

						     U_SB_ETH_RX_BD_INDEX),

			 bp->rx_ticks ? 0 : 1);



		/* HC_INDEX_C_ETH_TX_CQ_CONS */

		REG_WR8(bp, BAR_CSTRORM_INTMEM +
@@ -4489,25 +4485,14 @@ static void bnx2x_init_context(struct bnx2x *bp) 
		struct bnx2x_fastpath *fp = &bp->fp[i];

		u8 sb_id = FP_SB_ID(fp);



		context->xstorm_st_context.tx_bd_page_base_hi =

						U64_HI(fp->tx_desc_mapping);

		context->xstorm_st_context.tx_bd_page_base_lo =

						U64_LO(fp->tx_desc_mapping);

		context->xstorm_st_context.db_data_addr_hi =

						U64_HI(fp->tx_prods_mapping);

		context->xstorm_st_context.db_data_addr_lo =

						U64_LO(fp->tx_prods_mapping);

		context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) |

				XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);



		context->ustorm_st_context.common.sb_index_numbers =

						BNX2X_RX_SB_INDEX_NUM;

		context->ustorm_st_context.common.clientId = FP_CL_ID(fp);

		context->ustorm_st_context.common.status_block_id = sb_id;

		context->ustorm_st_context.common.flags =

			USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;

		context->ustorm_st_context.common.mc_alignment_size =

			BCM_RX_ETH_PAYLOAD_ALIGN;

		context->ustorm_st_context.common.mc_alignment_log_size =

			6 /*BCM_RX_ETH_PAYLOAD_ALIGN*/;

		context->ustorm_st_context.common.bd_buff_size =

						bp->rx_buf_size;

		context->ustorm_st_context.common.bd_page_base_hi =
@@ -4519,13 +4504,29 @@ static void bnx2x_init_context(struct bnx2x *bp) 
				(USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |

				 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);

			context->ustorm_st_context.common.sge_buff_size =

					(u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);

				(u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE,

					 (u32)0xffff);

			context->ustorm_st_context.common.sge_page_base_hi =

						U64_HI(fp->rx_sge_mapping);

			context->ustorm_st_context.common.sge_page_base_lo =

						U64_LO(fp->rx_sge_mapping);

		}



		context->ustorm_ag_context.cdu_usage =

			CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),

					       CDU_REGION_NUMBER_UCM_AG,

					       ETH_CONNECTION_TYPE);



		context->xstorm_st_context.tx_bd_page_base_hi =

						U64_HI(fp->tx_desc_mapping);

		context->xstorm_st_context.tx_bd_page_base_lo =

						U64_LO(fp->tx_desc_mapping);

		context->xstorm_st_context.db_data_addr_hi =

						U64_HI(fp->tx_prods_mapping);

		context->xstorm_st_context.db_data_addr_lo =

						U64_LO(fp->tx_prods_mapping);

		context->xstorm_st_context.statistics_data = (fp->cl_id |

				XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);

		context->cstorm_st_context.sb_index_number =

						C_SB_ETH_TX_CQ_INDEX;

		context->cstorm_st_context.status_block_id = sb_id;
@@ -4534,10 +4535,6 @@ static void bnx2x_init_context(struct bnx2x *bp) 
			CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),

					       CDU_REGION_NUMBER_XCM_AG,

					       ETH_CONNECTION_TYPE);

		context->ustorm_ag_context.cdu_usage =

			CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),

					       CDU_REGION_NUMBER_UCM_AG,

					       ETH_CONNECTION_TYPE);

	}

}
@@ -4569,7 +4566,7 @@ static void bnx2x_set_client_config(struct bnx2x *bp) 
#ifdef BCM_VLAN

	if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {

		tstorm_client.config_flags |=

				TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;

				TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;

		DP(NETIF_MSG_IFUP, "vlan removal enabled\n");

	}

#endif
@@ -4690,6 +4687,9 @@ static void bnx2x_init_internal_func(struct bnx2x *bp) 
		tstorm_config.config_flags = MULTI_FLAGS;

		tstorm_config.rss_result_mask = MULTI_MASK;

	}

	if (IS_E1HMF(bp))

		tstorm_config.config_flags |=

				TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;



	tstorm_config.leading_client_id = BP_L_ID(bp);
@@ -5338,7 +5338,6 @@ static int bnx2x_init_common(struct bnx2x *bp) 
		REG_WR(bp, i, 0xc0cac01a);

		/* TODO: replace with something meaningful */

	}

	if (CHIP_IS_E1H(bp))

	bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);

	REG_WR(bp, SRC_REG_SOFT_RST, 0);
@@ -5358,6 +5357,11 @@ static int bnx2x_init_common(struct bnx2x *bp) 


	bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);

	REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);

	/* enable context validation interrupt from CFC */

	REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);



	/* set the thresholds to prevent CFC/CDU race */

	REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);



	bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);

	bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
@@ -5485,6 +5489,8 @@ static int bnx2x_init_port(struct bnx2x *bp) 
	REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));

#endif

	/* Port CMs come here */

	bnx2x_init_block(bp, (port ? XCM_PORT1_START : XCM_PORT0_START),

			     (port ? XCM_PORT1_END : XCM_PORT0_END));



	/* Port QM comes here */

#ifdef BCM_ISCSI
@@ -5675,9 +5681,6 @@ static int bnx2x_init_func(struct bnx2x *bp) 
	}

	bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);



	if (CHIP_IS_E1H(bp))

		REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func);



	/* Reset PCIE errors for debug */

	REG_WR(bp, 0x2114, 0xffffffff);

	REG_WR(bp, 0x2120, 0xffffffff);
@@ -6171,7 +6174,7 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set) 
	 * unicasts 0-31:port0 32-63:port1

	 * multicast 64-127:port0 128-191:port1

	 */

	config->hdr.length_6b = 2;

	config->hdr.length = 2;

	config->hdr.offset = port ? 32 : 0;

	config->hdr.client_id = BP_CL_ID(bp);

	config->hdr.reserved1 = 0;
@@ -6229,7 +6232,7 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set) 
	 * unicasts: by func number

	 * multicast: 20+FUNC*20, 20 each

	 */

	config->hdr.length_6b = 1;

	config->hdr.length = 1;

	config->hdr.offset = BP_FUNC(bp);

	config->hdr.client_id = BP_CL_ID(bp);

	config->hdr.reserved1 = 0;
@@ -6764,10 +6767,10 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) 


		bnx2x_set_mac_addr_e1(bp, 0);



		for (i = 0; i < config->hdr.length_6b; i++)

		for (i = 0; i < config->hdr.length; i++)

			CAM_INVALIDATE(config->config_table[i]);



		config->hdr.length_6b = i;

		config->hdr.length = i;

		if (CHIP_REV_IS_SLOW(bp))

			config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);

		else
@@ -8959,7 +8962,7 @@ static int bnx2x_test_intr(struct bnx2x *bp) 
	if (!netif_running(bp->dev))

		return -ENODEV;



	config->hdr.length_6b = 0;

	config->hdr.length = 0;

	if (CHIP_IS_E1(bp))

		config->hdr.offset = (BP_PORT(bp) ? 32 : 0);

	else
@@ -9921,7 +9924,7 @@ static void bnx2x_set_rx_mode(struct net_device *dev) 
				   config->config_table[i].

						cam_entry.lsb_mac_addr);

			}

			old = config->hdr.length_6b;

			old = config->hdr.length;

			if (old > i) {

				for (; i < old; i++) {

					if (CAM_IS_INVALID(config->
@@ -9940,9 +9943,9 @@ static void bnx2x_set_rx_mode(struct net_device *dev) 
			else

				offset = BNX2X_MAX_MULTICAST*(1 + port);



			config->hdr.length_6b = i;

			config->hdr.length = i;

			config->hdr.offset = offset;

			config->hdr.client_id = BP_CL_ID(bp);

			config->hdr.client_id = bp->fp->cl_id;

			config->hdr.reserved1 = 0;



			bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
@@ -10487,7 +10490,7 @@ static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 
		struct mac_configuration_cmd *config =

						bnx2x_sp(bp, mcast_config);



		for (i = 0; i < config->hdr.length_6b; i++)

		for (i = 0; i < config->hdr.length; i++)

			CAM_INVALIDATE(config->config_table[i]);

	}

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