Commit 8d8c82b6 authored by Joseph Gravenor's avatar Joseph Gravenor Committed by Alex Deucher
Browse files

drm/amd/display: add worst case dcc meta pitch to fake plane 



[why]
When we have single channel memory, we can not light up 2 4k displays
with a 1080p edp, because we don't have enough bw by a small margin.
this small margin comes from dcc meta being too large. We however don't
have this dcc meta when we create fake planes so, before the flip we
will not filter out the mode for 2 4k displays with a 1080p edp

[how]
Change get_default_swizzle_mode to something more general so we don't
end up with a separate function for every missing field in the fake
plane. Add a reasonable dcc meta to the fake plane when it is filled in,
so we filter out modes that don't have enough bandwidth. To do this, we
take the screen width and align it to 1024(8k 60)

Signed-off-by: default avatarJoseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c14b726e

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+2 −2
Original line number Diff line number Diff line
@@ -2171,10 +2171,10 @@ enum dc_status dc_validate_global_state( 
			if (pipe_ctx->stream != stream)

				continue;



			if (dc->res_pool->funcs->get_default_swizzle_mode &&

			if (dc->res_pool->funcs->patch_unknown_plane_state &&

					pipe_ctx->plane_state &&

					pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {

				result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);

				result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);

				if (result != DC_OK)

					return result;

			}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+2 −2
Original line number Diff line number Diff line
@@ -1233,7 +1233,7 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont 
	return DC_OK;

}



static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state)

static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)

{

	enum dc_status result = DC_OK;
@@ -1295,7 +1295,7 @@ static const struct resource_funcs dcn10_res_pool_funcs = { 
	.validate_plane = dcn10_validate_plane,

	.validate_global = dcn10_validate_global,

	.add_stream_to_ctx = dcn10_add_stream_to_ctx,

	.get_default_swizzle_mode = dcn10_get_default_swizzle_mode,

	.patch_unknown_plane_state = dcn10_patch_unknown_plane_state,

	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link

};

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+2 −2
Original line number Diff line number Diff line
@@ -3027,7 +3027,7 @@ static struct dc_cap_funcs cap_funcs = { 
};





enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)

{

	enum dc_status result = DC_OK;
@@ -3053,7 +3053,7 @@ static struct resource_funcs dcn20_res_pool_funcs = { 
	.add_stream_to_ctx = dcn20_add_stream_to_ctx,

	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,

	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,

	.get_default_swizzle_mode = dcn20_get_default_swizzle_mode,

	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,

	.set_mcif_arb_params = dcn20_set_mcif_arb_params,

	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,

	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h

+1 −1
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state 
enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);

enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);



void dcn20_patch_bounding_box(

		struct dc *dc,

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+14 −1
Original line number Diff line number Diff line
@@ -1730,6 +1730,19 @@ static int dcn21_populate_dml_pipes_from_context( 
	return pipe_cnt;

}



enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)

{

	enum dc_status result = DC_OK;



	if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {

		plane_state->dcc.enable = 1;

		/* align to our worst case block width */

		plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;

	}

	result = dcn20_patch_unknown_plane_state(plane_state);

	return result;

}



static struct resource_funcs dcn21_res_pool_funcs = {

	.destroy = dcn21_destroy_resource_pool,

	.link_enc_create = dcn21_link_encoder_create,
@@ -1739,7 +1752,7 @@ static struct resource_funcs dcn21_res_pool_funcs = { 
	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,

	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,

	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,

	.get_default_swizzle_mode = dcn20_get_default_swizzle_mode,

	.patch_unknown_plane_state = dcn21_patch_unknown_plane_state,

	.set_mcif_arb_params = dcn20_set_mcif_arb_params,

	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,

	.update_bw_bounding_box = update_bw_bounding_box

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