Commit 8d818c10 authored by Horia Geantă's avatar Horia Geantă Committed by Herbert Xu
Browse files

crypto: caam/qi2 - add DPAA2-CAAM driver 



Add CAAM driver that works using the DPSECI backend, i.e. manages
DPSECI DPAA2 objects sitting on the Management Complex (MC) fsl-mc bus.

Data transfers (crypto requests) are sent/received to/from CAAM crypto
engine via Queue Interface (v2), this being similar to existing caam/qi.
OTOH, configuration/setup (obtaining virtual queue IDs, authorization
etc.) is done by sending commands to the MC f/w.

Note that the CAAM accelerator included in DPAA2 platforms still has
Job Rings. However, the driver being added does not handle access
via this backend. Kconfig & Makefile are updated such that DPAA2-CAAM
(a.k.a. "caam/qi2") driver does not depend on caam/jr or caam/qi
backends - which rely on platform bus support (ctrl.c).

Support for the following aead and authenc algorithms is also added
in this patch:
-aead:
gcm(aes)
rfc4106(gcm(aes))
rfc4543(gcm(aes))
-authenc:
authenc(hmac({md5,sha*}),cbc({aes,des,des3_ede}))
echainiv(authenc(hmac({md5,sha*}),cbc({aes,des,des3_ede})))
authenc(hmac({md5,sha*}),rfc3686(ctr(aes))
seqiv(authenc(hmac({md5,sha*}),rfc3686(ctr(aes)))

Signed-off-by: default avatarHoria Geantă <horia.geanta@nxp.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 94cebd9d

drivers/crypto/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/ 
obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/

obj-$(CONFIG_CRYPTO_DEV_NITROX) += cavium/nitrox/

obj-$(CONFIG_CRYPTO_DEV_EXYNOS_RNG) += exynos-rng.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += caam/

obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o

obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o

obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o

drivers/crypto/caam/Kconfig

+34 −15
Original line number Diff line number Diff line 
config CRYPTO_DEV_FSL_CAAM_COMMON

	tristate



config CRYPTO_DEV_FSL_CAAM

	tristate "Freescale CAAM-Multicore driver backend"

	tristate "Freescale CAAM-Multicore platform driver backend"

	depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE

	select SOC_BUS

	select CRYPTO_DEV_FSL_CAAM_COMMON

	help

	  Enables the driver module for Freescale's Cryptographic Accelerator

	  and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
@@ -12,9 +16,16 @@ config CRYPTO_DEV_FSL_CAAM 
	  To compile this driver as a module, choose M here: the module

	  will be called caam.



if CRYPTO_DEV_FSL_CAAM



config CRYPTO_DEV_FSL_CAAM_DEBUG

	bool "Enable debug output in CAAM driver"

	help

	  Selecting this will enable printing of various debug

	  information in the CAAM driver.



config CRYPTO_DEV_FSL_CAAM_JR

	tristate "Freescale CAAM Job Ring driver backend"

	depends on CRYPTO_DEV_FSL_CAAM

	default y

	help

	  Enables the driver module for Job Rings which are part of
@@ -25,9 +36,10 @@ config CRYPTO_DEV_FSL_CAAM_JR 
	  To compile this driver as a module, choose M here: the module

	  will be called caam_jr.



if CRYPTO_DEV_FSL_CAAM_JR



config CRYPTO_DEV_FSL_CAAM_RINGSIZE

	int "Job Ring size"

	depends on CRYPTO_DEV_FSL_CAAM_JR

	range 2 9

	default "9"

	help
@@ -45,7 +57,6 @@ config CRYPTO_DEV_FSL_CAAM_RINGSIZE 


config CRYPTO_DEV_FSL_CAAM_INTC

	bool "Job Ring interrupt coalescing"

	depends on CRYPTO_DEV_FSL_CAAM_JR

	help

	  Enable the Job Ring's interrupt coalescing feature.
@@ -75,7 +86,6 @@ config CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD 


config CRYPTO_DEV_FSL_CAAM_CRYPTO_API

	tristate "Register algorithm implementations with the Crypto API"

	depends on CRYPTO_DEV_FSL_CAAM_JR

	default y

	select CRYPTO_AEAD

	select CRYPTO_AUTHENC
@@ -90,7 +100,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API 


config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI

	tristate "Queue Interface as Crypto API backend"

	depends on CRYPTO_DEV_FSL_CAAM_JR && FSL_DPAA && NET

	depends on FSL_DPAA && NET

	default y

	select CRYPTO_AUTHENC

	select CRYPTO_BLKCIPHER
@@ -107,7 +117,6 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI 


config CRYPTO_DEV_FSL_CAAM_AHASH_API

	tristate "Register hash algorithm implementations with Crypto API"

	depends on CRYPTO_DEV_FSL_CAAM_JR

	default y

	select CRYPTO_HASH

	help
@@ -119,7 +128,6 @@ config CRYPTO_DEV_FSL_CAAM_AHASH_API 


config CRYPTO_DEV_FSL_CAAM_PKC_API

        tristate "Register public key cryptography implementations with Crypto API"

        depends on CRYPTO_DEV_FSL_CAAM_JR

        default y

        select CRYPTO_RSA

        help
@@ -131,7 +139,6 @@ config CRYPTO_DEV_FSL_CAAM_PKC_API 


config CRYPTO_DEV_FSL_CAAM_RNG_API

	tristate "Register caam device for hwrng API"

	depends on CRYPTO_DEV_FSL_CAAM_JR

	default y

	select CRYPTO_RNG

	select HW_RANDOM
@@ -142,13 +149,25 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API 
	  To compile this as a module, choose M here: the module

	  will be called caamrng.



config CRYPTO_DEV_FSL_CAAM_DEBUG

	bool "Enable debug output in CAAM driver"

	depends on CRYPTO_DEV_FSL_CAAM

endif # CRYPTO_DEV_FSL_CAAM_JR



endif # CRYPTO_DEV_FSL_CAAM



config CRYPTO_DEV_FSL_DPAA2_CAAM

	tristate "QorIQ DPAA2 CAAM (DPSECI) driver"

	depends on FSL_MC_DPIO

	select CRYPTO_DEV_FSL_CAAM_COMMON

	select CRYPTO_AUTHENC

	select CRYPTO_AEAD

	help

	  Selecting this will enable printing of various debug

	  information in the CAAM driver.

	  CAAM driver for QorIQ Data Path Acceleration Architecture 2.

	  It handles DPSECI DPAA2 objects that sit on the Management Complex

	  (MC) fsl-mc bus.



	  To compile this as a module, choose M here: the module

	  will be called dpaa2_caam.



config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC

	def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \

		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI)
 
		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI || \

		      CRYPTO_DEV_FSL_DPAA2_CAAM)

drivers/crypto/caam/Makefile

+8 −1
Original line number Diff line number Diff line
@@ -6,6 +6,9 @@ ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG), y) 
	ccflags-y := -DDEBUG

endif



ccflags-y += -DVERSION=\"\"



obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += error.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o

obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
@@ -16,9 +19,13 @@ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o 
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caam_pkc.o



caam-objs := ctrl.o

caam_jr-objs := jr.o key_gen.o error.o

caam_jr-objs := jr.o key_gen.o

caam_pkc-y := caampkc.o pkc_desc.o

ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),)

	ccflags-y += -DCONFIG_CAAM_QI

	caam-objs += qi.o

endif



obj-$(CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM) += dpaa2_caam.o



dpaa2_caam-y    := caamalg_qi2.o dpseci.o

drivers/crypto/caam/caamalg_qi2.c

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+2872 −0

File added.

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drivers/crypto/caam/caamalg_qi2.h

0 → 100644
+189 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */

/*

 * Copyright 2015-2016 Freescale Semiconductor Inc.

 * Copyright 2017-2018 NXP

 */



#ifndef _CAAMALG_QI2_H_

#define _CAAMALG_QI2_H_



#include <soc/fsl/dpaa2-io.h>

#include <soc/fsl/dpaa2-fd.h>

#include <linux/threads.h>

#include "dpseci.h"

#include "desc_constr.h"



#define DPAA2_CAAM_STORE_SIZE	16

/* NAPI weight *must* be a multiple of the store size. */

#define DPAA2_CAAM_NAPI_WEIGHT	64



/* The congestion entrance threshold was chosen so that on LS2088

 * we support the maximum throughput for the available memory

 */

#define DPAA2_SEC_CONG_ENTRY_THRESH	(128 * 1024 * 1024)

#define DPAA2_SEC_CONG_EXIT_THRESH	(DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)



/**

 * dpaa2_caam_priv - driver private data

 * @dpseci_id: DPSECI object unique ID

 * @major_ver: DPSECI major version

 * @minor_ver: DPSECI minor version

 * @dpseci_attr: DPSECI attributes

 * @sec_attr: SEC engine attributes

 * @rx_queue_attr: array of Rx queue attributes

 * @tx_queue_attr: array of Tx queue attributes

 * @cscn_mem: pointer to memory region containing the congestion SCN

 *	it's size is larger than to accommodate alignment

 * @cscn_mem_aligned: pointer to congestion SCN; it is computed as

 *	PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)

 * @cscn_dma: dma address used by the QMAN to write CSCN messages

 * @dev: device associated with the DPSECI object

 * @mc_io: pointer to MC portal's I/O object

 * @domain: IOMMU domain

 * @ppriv: per CPU pointers to privata data

 */

struct dpaa2_caam_priv {

	int dpsec_id;



	u16 major_ver;

	u16 minor_ver;



	struct dpseci_attr dpseci_attr;

	struct dpseci_sec_attr sec_attr;

	struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];

	struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];

	int num_pairs;



	/* congestion */

	void *cscn_mem;

	void *cscn_mem_aligned;

	dma_addr_t cscn_dma;



	struct device *dev;

	struct fsl_mc_io *mc_io;

	struct iommu_domain *domain;



	struct dpaa2_caam_priv_per_cpu __percpu *ppriv;

};



/**

 * dpaa2_caam_priv_per_cpu - per CPU private data

 * @napi: napi structure

 * @net_dev: netdev used by napi

 * @req_fqid: (virtual) request (Tx / enqueue) FQID

 * @rsp_fqid: (virtual) response (Rx / dequeue) FQID

 * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr

 * @nctx: notification context of response FQ

 * @store: where dequeued frames are stored

 * @priv: backpointer to dpaa2_caam_priv

 */

struct dpaa2_caam_priv_per_cpu {

	struct napi_struct napi;

	struct net_device net_dev;

	int req_fqid;

	int rsp_fqid;

	int prio;

	struct dpaa2_io_notification_ctx nctx;

	struct dpaa2_io_store *store;

	struct dpaa2_caam_priv *priv;

};



/*

 * The CAAM QI hardware constructs a job descriptor which points

 * to shared descriptor (as pointed by context_a of FQ to CAAM).

 * When the job descriptor is executed by deco, the whole job

 * descriptor together with shared descriptor gets loaded in

 * deco buffer which is 64 words long (each 32-bit).

 *

 * The job descriptor constructed by QI hardware has layout:

 *

 *	HEADER		(1 word)

 *	Shdesc ptr	(1 or 2 words)

 *	SEQ_OUT_PTR	(1 word)

 *	Out ptr		(1 or 2 words)

 *	Out length	(1 word)

 *	SEQ_IN_PTR	(1 word)

 *	In ptr		(1 or 2 words)

 *	In length	(1 word)

 *

 * The shdesc ptr is used to fetch shared descriptor contents

 * into deco buffer.

 *

 * Apart from shdesc contents, the total number of words that

 * get loaded in deco buffer are '8' or '11'. The remaining words

 * in deco buffer can be used for storing shared descriptor.

 */

#define MAX_SDLEN	((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)



/* Length of a single buffer in the QI driver memory cache */

#define CAAM_QI_MEMCACHE_SIZE	512



/*

 * aead_edesc - s/w-extended aead descriptor

 * @src_nents: number of segments in input scatterlist

 * @dst_nents: number of segments in output scatterlist

 * @iv_dma: dma address of iv for checking continuity and link table

 * @qm_sg_bytes: length of dma mapped h/w link table

 * @qm_sg_dma: bus physical mapped address of h/w link table

 * @assoclen: associated data length, in CAAM endianness

 * @assoclen_dma: bus physical mapped address of req->assoclen

 * @sgt: the h/w link table, followed by IV

 */

struct aead_edesc {

	int src_nents;

	int dst_nents;

	dma_addr_t iv_dma;

	int qm_sg_bytes;

	dma_addr_t qm_sg_dma;

	unsigned int assoclen;

	dma_addr_t assoclen_dma;

	struct dpaa2_sg_entry sgt[0];

};



/**

 * caam_flc - Flow Context (FLC)

 * @flc: Flow Context options

 * @sh_desc: Shared Descriptor

 */

struct caam_flc {

	u32 flc[16];

	u32 sh_desc[MAX_SDLEN];

} ____cacheline_aligned;



enum optype {

	ENCRYPT = 0,

	DECRYPT,

	NUM_OP

};



/**

 * caam_request - the request structure the driver application should fill while

 *                submitting a job to driver.

 * @fd_flt: Frame list table defining input and output

 *          fd_flt[0] - FLE pointing to output buffer

 *          fd_flt[1] - FLE pointing to input buffer

 * @fd_flt_dma: DMA address for the frame list table

 * @flc: Flow Context

 * @flc_dma: I/O virtual address of Flow Context

 * @cbk: Callback function to invoke when job is completed

 * @ctx: arbit context attached with request by the application

 * @edesc: extended descriptor; points to aead_edesc

 */

struct caam_request {

	struct dpaa2_fl_entry fd_flt[2];

	dma_addr_t fd_flt_dma;

	struct caam_flc *flc;

	dma_addr_t flc_dma;

	void (*cbk)(void *ctx, u32 err);

	void *ctx;

	void *edesc;

};



/**

 * dpaa2_caam_enqueue() - enqueue a crypto request

 * @dev: device associated with the DPSECI object

 * @req: pointer to caam_request

 */

int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);



#endif	/* _CAAMALG_QI2_H_ */

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