Commit 8d36fdcc authored by Kazuya Mizuguchi's avatar Kazuya Mizuguchi Committed by Geert Uytterhoeven
Browse files

clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI 



According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.

Signed-off-by: default avatarKazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 4aeed945

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -165,8 +165,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { 
	DEF_MOD("vspd0",		 623,	R8A774A1_CLK_S0D2),

	DEF_MOD("vspb",			 626,	R8A774A1_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A774A1_CLK_S0D1),

	DEF_MOD("ehci1",		 702,	R8A774A1_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A774A1_CLK_S3D4),

	DEF_MOD("ehci1",		 702,	R8A774A1_CLK_S3D2),

	DEF_MOD("ehci0",		 703,	R8A774A1_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A774A1_CLK_S3D4),

	DEF_MOD("csi20",		 714,	R8A774A1_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A774A1_CLK_CSI0),

drivers/clk/renesas/r8a774c0-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -178,7 +178,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { 
	DEF_MOD("vspb",			 626,	R8A774C0_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A774C0_CLK_S0D1),



	DEF_MOD("ehci0",		 703,	R8A774C0_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A774C0_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A774C0_CLK_S3D4),

	DEF_MOD("csi40",		 716,	R8A774C0_CLK_CSI0),

	DEF_MOD("du1",			 723,	R8A774C0_CLK_S1D1),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+4 −4
Original line number Diff line number Diff line
@@ -195,10 +195,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("vspi2",		 629,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("vspi1",		 630,	R8A7795_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A7795_CLK_S0D1),

	DEF_MOD("ehci3",		 700,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci3",		 700,	R8A7795_CLK_S3D2),

	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D2),

	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D2),

	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D4),

	DEF_MOD("hsusb3",		 705,	R8A7795_CLK_S3D4),

	DEF_MOD("csi21",		 713,	R8A7795_CLK_CSI0), /* ES1.x */

drivers/clk/renesas/r8a7796-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -177,8 +177,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("vspd0",		 623,	R8A7796_CLK_S0D2),

	DEF_MOD("vspb",			 626,	R8A7796_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A7796_CLK_S0D1),

	DEF_MOD("ehci1",		 702,	R8A7796_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A7796_CLK_S3D4),

	DEF_MOD("ehci1",		 702,	R8A7796_CLK_S3D2),

	DEF_MOD("ehci0",		 703,	R8A7796_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A7796_CLK_S3D4),

	DEF_MOD("csi20",		 714,	R8A7796_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A7796_CLK_CSI0),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -175,8 +175,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 
	DEF_MOD("vspb",			626,	R8A77965_CLK_S0D1),

	DEF_MOD("vspi0",		631,	R8A77965_CLK_S0D1),



	DEF_MOD("ehci1",		702,	R8A77965_CLK_S3D4),

	DEF_MOD("ehci0",		703,	R8A77965_CLK_S3D4),

	DEF_MOD("ehci1",		702,	R8A77965_CLK_S3D2),

	DEF_MOD("ehci0",		703,	R8A77965_CLK_S3D2),

	DEF_MOD("hsusb",		704,	R8A77965_CLK_S3D4),

	DEF_MOD("csi20",		714,	R8A77965_CLK_CSI0),

	DEF_MOD("csi40",		716,	R8A77965_CLK_CSI0),

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