spi: lantiq: Move interrupt control register offesets to SoC specific data structure (8d19d665) · Commits · 戴 / test

Address of Interrupt control registers are different on new chipsets. So move them to SoC specific data structure. Signed-off-by:

drivers/spi/spi-lantiq-ssc.c

+12 −8

Original line number	Diff line number	Diff line
		@@ -49,8 +49,6 @@
		#define LTQ_SPI_RXCNT 0x84
		#define LTQ_SPI_DMACON 0xec
		#define LTQ_SPI_IRNEN 0xf4
		#define LTQ_SPI_IRNICR 0xf8
		#define LTQ_SPI_IRNCR 0xfc

		#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
		#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
		@@ -160,6 +158,8 @@
		struct lantiq_ssc_hwcfg {
		unsigned int irnen_r;
		unsigned int irnen_t;
		unsigned int irncr;
		unsigned int irnicr;
		};

		struct lantiq_ssc_spi {
		@@ -794,11 +794,15 @@ static int lantiq_ssc_transfer_one(struct spi_master *master,
		static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
		.irnen_r = LTQ_SPI_IRNEN_R_XWAY,
		.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
		.irnicr = 0xF8,
		.irncr = 0xFC,
		};

		static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
		.irnen_r = LTQ_SPI_IRNEN_R_XRX,
		.irnen_t = LTQ_SPI_IRNEN_T_XRX,
		.irnicr = 0xF8,
		.irncr = 0xFC,
		};

		static const struct of_device_id lantiq_ssc_match[] = {