Commit 8cd84b70 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull more KVM updates from Paolo Bonzini:
 "PPC:
   - Improvements and bugfixes for secure VM support, giving reduced
     startup time and memory hotplug support.

   - Locking fixes in nested KVM code

   - Increase number of guests supported by HV KVM to 4094

   - Preliminary POWER10 support

  ARM:
   - Split the VHE and nVHE hypervisor code bases, build the EL2 code
     separately, allowing for the VHE code to now be built with
     instrumentation

   - Level-based TLB invalidation support

   - Restructure of the vcpu register storage to accomodate the NV code

   - Pointer Authentication available for guests on nVHE hosts

   - Simplification of the system register table parsing

   - MMU cleanups and fixes

   - A number of post-32bit cleanups and other fixes

  MIPS:
   - compilation fixes

  x86:
   - bugfixes

   - support for the SERIALIZE instruction"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (70 commits)
  KVM: MIPS/VZ: Fix build error caused by 'kvm_run' cleanup
  x86/kvm/hyper-v: Synic default SCONTROL MSR needs to be enabled
  MIPS: KVM: Convert a fallthrough comment to fallthrough
  MIPS: VZ: Only include loongson_regs.h for CPU_LOONGSON64
  x86: Expose SERIALIZE for supported cpuid
  KVM: x86: Don't attempt to load PDPTRs when 64-bit mode is enabled
  KVM: arm64: Move S1PTW S2 fault logic out of io_mem_abort()
  KVM: arm64: Don't skip cache maintenance for read-only memslots
  KVM: arm64: Handle data and instruction external aborts the same way
  KVM: arm64: Rename kvm_vcpu_dabt_isextabt()
  KVM: arm: Add trace name for ARM_NISV
  KVM: arm64: Ensure that all nVHE hyp code is in .hyp.text
  KVM: arm64: Substitute RANDOMIZE_BASE for HARDEN_EL2_VECTORS
  KVM: arm64: Make nVHE ASLR conditional on RANDOMIZE_BASE
  KVM: PPC: Book3S HV: Rework secure mem slot dropping
  KVM: PPC: Book3S HV: Move kvmppc_svm_page_out up
  KVM: PPC: Book3S HV: Migrate hot plugged memory
  KVM: PPC: Book3S HV: In H_SVM_INIT_DONE, migrate remaining normal-GFNs to secure-GFNs
  KVM: PPC: Book3S HV: Track the state GFNs associated with secure VMs
  KVM: PPC: Book3S HV: Disable page merging in H_SVM_INIT_START
  ...
parents 05a5b5d8 e792415c

Documentation/powerpc/ultravisor.rst

+3 −0
Original line number Diff line number Diff line
@@ -895,6 +895,7 @@ Return values 
    One of the following values:



	* H_SUCCESS	 on success.

        * H_STATE        if the VM is not in a position to switch to secure.



Description

~~~~~~~~~~~
@@ -933,6 +934,8 @@ Return values 
	* H_UNSUPPORTED		if called from the wrong context (e.g.

				from an SVM or before an H_SVM_INIT_START

				hypercall).

	* H_STATE		if the hypervisor could not successfully

                                transition the VM to Secure VM.



Description

~~~~~~~~~~~

arch/arm64/Kconfig

+1 −19
Original line number Diff line number Diff line
@@ -1182,22 +1182,6 @@ config HARDEN_BRANCH_PREDICTOR 


	  If unsure, say Y.



config HARDEN_EL2_VECTORS

	bool "Harden EL2 vector mapping against system register leak" if EXPERT

	default y

	help

	  Speculation attacks against some high-performance processors can

	  be used to leak privileged information such as the vector base

	  register, resulting in a potential defeat of the EL2 layout

	  randomization.



	  This config option will map the vectors to a fixed location,

	  independent of the EL2 code mapping, so that revealing VBAR_EL2

	  to an attacker does not give away any extra information. This

	  only gets enabled on affected CPUs.



	  If unsure, say Y.



config ARM64_SSBD

	bool "Speculative Store Bypass Disable" if EXPERT

	default y
@@ -1520,7 +1504,6 @@ menu "ARMv8.3 architectural features" 
config ARM64_PTR_AUTH

	bool "Enable support for pointer authentication"

	default y

	depends on !KVM || ARM64_VHE

	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC

	# Modern compilers insert a .note.gnu.property section note for PAC

	# which is only understood by binutils starting with version 2.33.1.
@@ -1547,8 +1530,7 @@ config ARM64_PTR_AUTH 


	  The feature is detected at runtime. If the feature is not present in

	  hardware it will not be advertised to userspace/KVM guest nor will it

	  be enabled. However, KVM guest also require VHE mode and hence

	  CONFIG_ARM64_VHE=y option to use this feature.

	  be enabled.



	  If the feature is present on the boot CPU but not on a late CPU, then

	  the late CPU will be parked. Also, if the boot CPU does not have

arch/arm64/include/asm/kvm_asm.h

+61 −14
Original line number Diff line number Diff line
@@ -42,33 +42,81 @@ 


#include <linux/mm.h>



/* Translate a kernel address of @sym into its equivalent linear mapping */

#define kvm_ksym_ref(sym)						\

/*

 * Translate name of a symbol defined in nVHE hyp to the name seen

 * by kernel proper. All nVHE symbols are prefixed by the build system

 * to avoid clashes with the VHE variants.

 */

#define kvm_nvhe_sym(sym)	__kvm_nvhe_##sym



#define DECLARE_KVM_VHE_SYM(sym)	extern char sym[]

#define DECLARE_KVM_NVHE_SYM(sym)	extern char kvm_nvhe_sym(sym)[]



/*

 * Define a pair of symbols sharing the same name but one defined in

 * VHE and the other in nVHE hyp implementations.

 */

#define DECLARE_KVM_HYP_SYM(sym)		\

	DECLARE_KVM_VHE_SYM(sym);		\

	DECLARE_KVM_NVHE_SYM(sym)



#define CHOOSE_VHE_SYM(sym)	sym

#define CHOOSE_NVHE_SYM(sym)	kvm_nvhe_sym(sym)



#ifndef __KVM_NVHE_HYPERVISOR__

/*

 * BIG FAT WARNINGS:

 *

 * - Don't be tempted to change the following is_kernel_in_hyp_mode()

 *   to has_vhe(). has_vhe() is implemented as a *final* capability,

 *   while this is used early at boot time, when the capabilities are

 *   not final yet....

 *

 * - Don't let the nVHE hypervisor have access to this, as it will

 *   pick the *wrong* symbol (yes, it runs at EL2...).

 */

#define CHOOSE_HYP_SYM(sym)	(is_kernel_in_hyp_mode() ? CHOOSE_VHE_SYM(sym) \

					   : CHOOSE_NVHE_SYM(sym))

#else

/* The nVHE hypervisor shouldn't even try to access anything */

extern void *__nvhe_undefined_symbol;

#define CHOOSE_HYP_SYM(sym)	__nvhe_undefined_symbol

#endif



/* Translate a kernel address @ptr into its equivalent linear mapping */

#define kvm_ksym_ref(ptr)						\

	({								\

		void *val = &sym;					\

		void *val = (ptr);					\

		if (!is_kernel_in_hyp_mode())				\

			val = lm_alias(&sym);				\

			val = lm_alias((ptr));				\

		val;							\

	 })

#define kvm_ksym_ref_nvhe(sym)	kvm_ksym_ref(kvm_nvhe_sym(sym))



struct kvm;

struct kvm_vcpu;

struct kvm_s2_mmu;



extern char __kvm_hyp_init[];

extern char __kvm_hyp_init_end[];

DECLARE_KVM_NVHE_SYM(__kvm_hyp_init);

DECLARE_KVM_HYP_SYM(__kvm_hyp_vector);

#define __kvm_hyp_init		CHOOSE_NVHE_SYM(__kvm_hyp_init)

#define __kvm_hyp_vector	CHOOSE_HYP_SYM(__kvm_hyp_vector)



extern char __kvm_hyp_vector[];

#ifdef CONFIG_KVM_INDIRECT_VECTORS

extern atomic_t arm64_el2_vector_last_slot;

DECLARE_KVM_HYP_SYM(__bp_harden_hyp_vecs);

#define __bp_harden_hyp_vecs	CHOOSE_HYP_SYM(__bp_harden_hyp_vecs)

#endif



extern void __kvm_flush_vm_context(void);

extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);

extern void __kvm_tlb_flush_vmid(struct kvm *kvm);

extern void __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu);

extern void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, phys_addr_t ipa,

				     int level);

extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu);

extern void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu);



extern void __kvm_timer_set_cntvoff(u64 cntvoff);



extern int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu);



extern int __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu);

extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);



extern void __kvm_enable_ssbs(void);
@@ -143,7 +191,6 @@ extern char __smccc_workaround_1_smc[__SMCCC_WORKAROUND_1_SMC_SZ]; 
.macro get_vcpu_ptr vcpu, ctxt

	get_host_ctxt \ctxt, \vcpu

	ldr	\vcpu, [\ctxt, #HOST_CONTEXT_VCPU]

	kern_hyp_va	\vcpu

.endm



#endif

arch/arm64/include/asm/kvm_coproc.h

+0 −8
Original line number Diff line number Diff line
@@ -19,14 +19,6 @@ struct kvm_sys_reg_table { 
	size_t num;

};



struct kvm_sys_reg_target_table {

	struct kvm_sys_reg_table table64;

	struct kvm_sys_reg_table table32;

};



void kvm_register_target_sys_reg_table(unsigned int target,

				       struct kvm_sys_reg_target_table *table);



int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);

int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);

int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);

arch/arm64/include/asm/kvm_emulate.h

+27 −48
Original line number Diff line number Diff line
@@ -124,33 +124,12 @@ static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr) 


static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)

{

	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;

}



static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)

{

	return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;

}



static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)

{

	if (vcpu->arch.sysregs_loaded_on_cpu)

		return read_sysreg_el1(SYS_ELR);

	else

		return *__vcpu_elr_el1(vcpu);

}



static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)

{

	if (vcpu->arch.sysregs_loaded_on_cpu)

		write_sysreg_el1(v, SYS_ELR);

	else

		*__vcpu_elr_el1(vcpu) = v;

	return (unsigned long *)&vcpu_gp_regs(vcpu)->pc;

}



static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)

{

	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;

	return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate;

}



static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
@@ -179,14 +158,14 @@ static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu) 
static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,

					 u8 reg_num)

{

	return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];

	return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];

}



static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,

				unsigned long val)

{

	if (reg_num != 31)

		vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;

		vcpu_gp_regs(vcpu)->regs[reg_num] = val;

}



static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
@@ -197,7 +176,7 @@ static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu) 
	if (vcpu->arch.sysregs_loaded_on_cpu)

		return read_sysreg_el1(SYS_SPSR);

	else

		return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];

		return __vcpu_sys_reg(vcpu, SPSR_EL1);

}



static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
@@ -210,7 +189,7 @@ static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v) 
	if (vcpu->arch.sysregs_loaded_on_cpu)

		write_sysreg_el1(v, SYS_SPSR);

	else

		vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;

		__vcpu_sys_reg(vcpu, SPSR_EL1) = v;

}



/*
@@ -259,14 +238,14 @@ static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu) 
	return mode != PSR_MODE_EL0t;

}



static __always_inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)

static __always_inline u32 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)

{

	return vcpu->arch.fault.esr_el2;

}



static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)

{

	u32 esr = kvm_vcpu_get_hsr(vcpu);

	u32 esr = kvm_vcpu_get_esr(vcpu);



	if (esr & ESR_ELx_CV)

		return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
@@ -291,64 +270,64 @@ static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu) 


static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;

	return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;

}



static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);

}



static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);

	return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);

}



static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);

}



static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SF);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);

}



static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)

{

	return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;

	return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;

}



static __always_inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);

}



static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR) ||

		kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */

}



static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);

}



static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)

{

	return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);

	return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);

}



/* This one is not specific to Data Abort */

static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);

	return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);

}



static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)

{

	return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));

	return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));

}



static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
@@ -358,15 +337,15 @@ static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu) 


static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;

	return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;

}



static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;

	return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE;

}



static __always_inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)

static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)

{

	switch (kvm_vcpu_trap_get_fault(vcpu)) {

	case FSC_SEA:
@@ -387,7 +366,7 @@ static __always_inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu) 


static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)

{

	u32 esr = kvm_vcpu_get_hsr(vcpu);

	u32 esr = kvm_vcpu_get_esr(vcpu);

	return ESR_ELx_SYS64_ISS_RT(esr);

}
@@ -516,14 +495,14 @@ static __always_inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_i 
 * Skip an instruction which has been emulated at hyp while most guest sysregs

 * are live.

 */

static __always_inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)

static __always_inline void __kvm_skip_instr(struct kvm_vcpu *vcpu)

{

	*vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);

	vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);

	vcpu_gp_regs(vcpu)->pstate = read_sysreg_el2(SYS_SPSR);



	kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));



	write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);

	write_sysreg_el2(vcpu_gp_regs(vcpu)->pstate, SYS_SPSR);

	write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);

}

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