iwlwifi: refactor rx register initialization

#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */

#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/

#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT	(20)

#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT	(4)

#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS	(20)

#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS	(4)

#define RX_RB_TIMEOUT	(0x10)

#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL         (0x00000000)

#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K   (0x00020000)

#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K   (0x00030000)

#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY              (0x00000004)

#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL    (0x00000000)

#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL  (0x00001000)

{

	int ret;

	unsigned long flags;

	unsigned int rb_size;

	u32 rb_size;

	const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */

	const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */

	spin_lock_irqsave(&priv->lock, flags);

	ret = iwl_grab_nic_access(priv);

	/* Tell device where to find RBD circular buffer in DRAM */

	iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,

			   rxq->dma_addr >> 8);

			   (u32)(rxq->dma_addr >> 8));

	/* Tell device where in DRAM to update its Rx status */

	iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,

			   (priv->shared_phys + priv->rb_closed_offset) >> 4);

	/* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */

	/* Enable Rx DMA

	 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set becuase of HW bug in

	 *      the credit mechanism in 5000 HW RX FIFO

	 * Direct rx interrupts to hosts

	 * Rx buffer size 4 or 8k

	 * RB timeout 0x10

	 * 256 RBDs

	 */

	iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,

			   FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |

			   FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |

			   FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |

			   rb_size|

			     /* 0x10 << 4 | */

			   (RX_QUEUE_SIZE_LOG <<

			      FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));

	/*

	 * iwl_write32(priv,CSR_INT_COAL_REG,0);

	 */

			   (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|

			   (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));

	iwl_release_nic_access(priv);

	iwl_write32(priv, CSR_INT_COALESCING, 0x40);

	spin_unlock_irqrestore(&priv->lock, flags);

	return 0;