Commit 8ccf0e20 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: determine USB C DP2 mode only when USB DP Alt is enabled 



[why]
When display is connected with a native DP port, DP2 mode register value
is a don't care. Driver mistakenly reduce max supported lane count to 2
lane based on the don't care value.

[how]
Add additional check only if USB C DP alt mode is enabled, we will
determine max lane count supported based on current mode.

Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4404b478

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+2 −2
Original line number Diff line number Diff line
@@ -682,7 +682,7 @@ static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) 
		       new_edid->raw_edid, new_edid->length) == 0);

}



static bool wait_for_alt_mode(struct dc_link *link)

static bool wait_for_entering_dp_alt_mode(struct dc_link *link)

{

	/**

	 * something is terribly wrong if time out is > 200ms. (5Hz)
@@ -836,7 +836,7 @@ static bool dc_link_detect_helper(struct dc_link *link, 
			/* wa HPD high coming too early*/

			if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {

				/* if alt mode times out, return false */

				if (!wait_for_alt_mode(link))

				if (!wait_for_entering_dp_alt_mode(link))

					return false;

			}

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+3 −12
Original line number Diff line number Diff line
@@ -1710,18 +1710,9 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down) 


static struct dc_link_settings get_max_link_cap(struct dc_link *link)

{

	/* Set Default link settings */

	struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,

			LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};



	/* Higher link settings based on feature supported */

	if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)

		max_link_cap.link_rate = LINK_RATE_HIGH2;



	if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)

		max_link_cap.link_rate = LINK_RATE_HIGH3;

	struct dc_link_settings max_link_cap = {0};



	if (link->link_enc->funcs->get_max_link_cap)

	/* get max link encoder capability */

	link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);



	/* Lower link settings based on sink's link cap */

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

+19 −1
Original line number Diff line number Diff line
@@ -118,7 +118,8 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { 
	.enable_hpd = dce110_link_encoder_enable_hpd,

	.disable_hpd = dce110_link_encoder_disable_hpd,

	.is_dig_enabled = dce110_is_dig_enabled,

	.destroy = dce110_link_encoder_destroy

	.destroy = dce110_link_encoder_destroy,

	.get_max_link_cap = dce110_link_encoder_get_max_link_cap

};



static enum bp_result link_transmitter_control(
@@ -1389,3 +1390,20 @@ void dce110_link_encoder_disable_hpd(struct link_encoder *enc) 


	set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);

}



void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,

	struct dc_link_settings *link_settings)

{

	/* Set Default link settings */

	struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,

			LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};



	/* Higher link settings based on feature supported */

	if (enc->features.flags.bits.IS_HBR2_CAPABLE)

		max_link_cap.link_rate = LINK_RATE_HIGH2;



	if (enc->features.flags.bits.IS_HBR3_CAPABLE)

		max_link_cap.link_rate = LINK_RATE_HIGH3;



	*link_settings = max_link_cap;

}

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

+3 −0
Original line number Diff line number Diff line
@@ -271,4 +271,7 @@ void dce110_psr_program_secondary_packet(struct link_encoder *enc, 


bool dce110_is_dig_enabled(struct link_encoder *enc);



void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,

	struct dc_link_settings *link_settings);



#endif /* __DC_LINK_ENCODER__DCE110_H__ */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

+18 −2
Original line number Diff line number Diff line
@@ -90,7 +90,8 @@ static const struct link_encoder_funcs dcn10_lnk_enc_funcs = { 
	.is_dig_enabled = dcn10_is_dig_enabled,

	.get_dig_frontend = dcn10_get_dig_frontend,

	.get_dig_mode = dcn10_get_dig_mode,

	.destroy = dcn10_link_encoder_destroy

	.destroy = dcn10_link_encoder_destroy,

	.get_max_link_cap = dcn10_link_encoder_get_max_link_cap,

};



static enum bp_result link_transmitter_control(
@@ -1370,7 +1371,6 @@ void dcn10_link_encoder_disable_hpd(struct link_encoder *enc) 
			DC_HPD_EN, 0);

}





#define AUX_REG(reg)\

	(enc10->aux_regs->reg)
@@ -1425,3 +1425,19 @@ enum signal_type dcn10_get_dig_mode( 
	return SIGNAL_TYPE_NONE;

}



void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,

	struct dc_link_settings *link_settings)

{

	/* Set Default link settings */

	struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,

			LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};



	/* Higher link settings based on feature supported */

	if (enc->features.flags.bits.IS_HBR2_CAPABLE)

		max_link_cap.link_rate = LINK_RATE_HIGH2;



	if (enc->features.flags.bits.IS_HBR3_CAPABLE)

		max_link_cap.link_rate = LINK_RATE_HIGH3;



	*link_settings = max_link_cap;

}

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