ARM: socfpga: dts: Add div-reg to the main_pll clocks

- fixed-divider : If clocks have a fixed divider value, use this property.

- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register

        and the bit index.

- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,

        and width.

- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains

	the divider register, bit shift, and width.

- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls

	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second

	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							fixed-divider = <2>;

							div-reg = <0xe0 0 9>;

							reg = <0x48>;

						};

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							fixed-divider = <4>;

							div-reg = <0xe4 0 9>;

							reg = <0x4C>;

						};

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							fixed-divider = <4>;

							div-reg = <0xe8 0 9>;

							reg = <0x50>;

						};