Commit 8c9b2e32 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux into drm-next 

New tree with the INFO ioctl merge fixed up.  This also adds a couple
of additional minor fixes.

A few more changes for 3.14, mostly just bug fixes.  Note that:
drm/radeon: add query to fetch the max engine clock.
will conflict with 3.13 final, but the fix is pretty obvious.

* 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux: (22 commits)
  drm/radeon: add UVD support for OLAND
  drm/radeon: fix minor typos in si_dpm.c
  drm/radeon: set the full cache bit for fences on r7xx+
  drm/radeon: fix surface sync in fence on cayman (v2)
  drm/radeon/dpm: disable mclk switching on desktop RV770
  drm/radeon: fix endian handling in radeon_atom_init_mc_reg_table
  drm/radeon: write gfx pg bases even when gfx pg is disabled
  drm/radeon: bail early from enable ss in certain cases
  drm/radeon: handle ss percentage divider properly
  drm/radeon: add query to fetch the max engine clock (v2)
  drm/radeon/dp: sleep after powering up the display
  drm/radeon/dp: use usleep_range rather than udelay
  drm/radeon/dp: bump i2c-over-aux retries to 7
  drm/radeon: disable ss on DP for DCE3.x
  drm/radeon/cik: use hw defaults for TC_CFG registers
  drm/radeon: disable dpm on BTC
  drm/radeon/cik: use WAIT_REG_MEM special op for CP HDP flush
  drm/radeon/cik: use POLL_REG_MEM special op for sDMA HDP flush
  drm/radeon: consolidate sdma hdp flushing code for CIK
  drm/radeon: consolidate cp hdp flushing code for CIK
  ...
parents cfd72a4c 5d029339

drivers/gpu/drm/radeon/atombios_crtc.c

+21 −11
Original line number Diff line number Diff line
@@ -423,7 +423,17 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev, 
	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);

	union atom_enable_ss args;



	if (!enable) {

	if (enable) {

		/* Don't mess with SS if percentage is 0 or external ss.

		 * SS is already disabled previously, and disabling it

		 * again can cause display problems if the pll is already

		 * programmed.

		 */

		if (ss->percentage == 0)

			return;

		if (ss->type & ATOM_EXTERNAL_SS_MASK)

			return;

	} else {

		for (i = 0; i < rdev->num_crtc; i++) {

			if (rdev->mode_info.crtcs[i] &&

			    rdev->mode_info.crtcs[i]->enabled &&
@@ -459,8 +469,6 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev, 
		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);

		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);

		args.v3.ucEnable = enable;

		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))

			args.v3.ucEnable = ATOM_DISABLE;

	} else if (ASIC_IS_DCE4(rdev)) {

		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
@@ -480,8 +488,6 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev, 
		args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);

		args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);

		args.v2.ucEnable = enable;

		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))

			args.v2.ucEnable = ATOM_DISABLE;

	} else if (ASIC_IS_DCE3(rdev)) {

		args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
@@ -503,8 +509,7 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev, 
		args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;

		args.lvds_ss_2.ucEnable = enable;

	} else {

		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||

		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {

		if (enable == ATOM_DISABLE) {

			atombios_disable_ss(rdev, pll_id);

			return;

		}
@@ -938,12 +943,15 @@ static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_ 
							radeon_atombios_get_ppll_ss_info(rdev,

											 &radeon_crtc->ss,

											 ATOM_DP_SS_ID1);

				} else

				} else {

					radeon_crtc->ss_enabled =

						radeon_atombios_get_ppll_ss_info(rdev,

										 &radeon_crtc->ss,

										 ATOM_DP_SS_ID1);

				}

				/* disable spread spectrum on DCE3 DP */

				radeon_crtc->ss_enabled = false;

			}

			break;

		case ATOM_ENCODER_MODE_LVDS:

			if (ASIC_IS_DCE4(rdev))
@@ -1039,15 +1047,17 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 
		/* calculate ss amount and step size */

		if (ASIC_IS_DCE4(rdev)) {

			u32 step_size;

			u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000;

			u32 amount = (((fb_div * 10) + frac_fb_div) *

				      (u32)radeon_crtc->ss.percentage) /

				(100 * (u32)radeon_crtc->ss.percentage_divider);

			radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;

			radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &

				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;

			if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)

				step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /

				step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

					(125 * 25 * pll->reference_freq / 100);

			else

				step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /

				step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

					(125 * 25 * pll->reference_freq / 100);

			radeon_crtc->ss.step = step_size;

		}

drivers/gpu/drm/radeon/atombios_dp.c

+10 −8
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 
	msg[3] = (msg_bytes << 4) | (send_bytes - 1);

	memcpy(&msg[4], send, send_bytes);



	for (retry = 0; retry < 4; retry++) {

	for (retry = 0; retry < 7; retry++) {

		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,

					    msg, msg_bytes, NULL, 0, delay, &ack);

		if (ret == -EBUSY)
@@ -172,7 +172,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 
		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)

			return send_bytes;

		else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)

			udelay(400);

			usleep_range(400, 500);

		else

			return -EIO;

	}
@@ -195,7 +195,7 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 
	msg[2] = DP_AUX_NATIVE_READ << 4;

	msg[3] = (msg_bytes << 4) | (recv_bytes - 1);



	for (retry = 0; retry < 4; retry++) {

	for (retry = 0; retry < 7; retry++) {

		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,

					    msg, msg_bytes, recv, recv_bytes, delay, &ack);

		if (ret == -EBUSY)
@@ -206,7 +206,7 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 
		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)

			return ret;

		else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)

			udelay(400);

			usleep_range(400, 500);

		else if (ret == 0)

			return -EPROTO;

		else
@@ -274,7 +274,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 
		break;

	}



	for (retry = 0; retry < 4; retry++) {

	for (retry = 0; retry < 7; retry++) {

		ret = radeon_process_aux_ch(auxch,

					    msg, msg_bytes, reply, reply_bytes, 0, &ack);

		if (ret == -EBUSY)
@@ -295,7 +295,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 
			return -EREMOTEIO;

		case DP_AUX_NATIVE_REPLY_DEFER:

			DRM_DEBUG_KMS("aux_ch native defer\n");

			udelay(400);

			usleep_range(500, 600);

			continue;

		default:

			DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
@@ -312,7 +312,7 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 
			return -EREMOTEIO;

		case DP_AUX_I2C_REPLY_DEFER:

			DRM_DEBUG_KMS("aux_i2c defer\n");

			udelay(400);

			usleep_range(400, 500);

			break;

		default:

			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
@@ -673,9 +673,11 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 
	u8 tmp;



	/* power up the sink */

	if (dp_info->dpcd[0] >= 0x11)

	if (dp_info->dpcd[0] >= 0x11) {

		radeon_write_dpcd_reg(dp_info->radeon_connector,

				      DP_SET_POWER, DP_SET_POWER_D0);

		usleep_range(1000, 2000);

	}



	/* possibly enable downspread on the sink */

	if (dp_info->dpcd[3] & 0x1)

drivers/gpu/drm/radeon/cik.c

+48 −47
Original line number Diff line number Diff line
@@ -3486,6 +3486,51 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 
	return r;

}



/**

 * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp

 *

 * @rdev: radeon_device pointer

 * @ridx: radeon ring index

 *

 * Emits an hdp flush on the cp.

 */

static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,

				       int ridx)

{

	struct radeon_ring *ring = &rdev->ring[ridx];

	u32 ref_and_mask;



	switch (ring->idx) {

	case CAYMAN_RING_TYPE_CP1_INDEX:

	case CAYMAN_RING_TYPE_CP2_INDEX:

	default:

		switch (ring->me) {

		case 0:

			ref_and_mask = CP2 << ring->pipe;

			break;

		case 1:

			ref_and_mask = CP6 << ring->pipe;

			break;

		default:

			return;

		}

		break;

	case RADEON_RING_TYPE_GFX_INDEX:

		ref_and_mask = CP0;

		break;

	}



	radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

	radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */

				 WAIT_REG_MEM_FUNCTION(3) |  /* == */

				 WAIT_REG_MEM_ENGINE(1)));   /* pfp */

	radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);

	radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);

	radeon_ring_write(ring, ref_and_mask);

	radeon_ring_write(ring, ref_and_mask);

	radeon_ring_write(ring, 0x20); /* poll interval */

}



/**

 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring

 *
@@ -3512,15 +3557,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 
	radeon_ring_write(ring, fence->seq);

	radeon_ring_write(ring, 0);

	/* HDP flush */

	/* We should be using the new WAIT_REG_MEM special op packet here

	 * but it causes the CP to hang

	 */

	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |

				 WRITE_DATA_DST_SEL(0)));

	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 0);

	cik_hdp_flush_cp_ring_emit(rdev, fence->ring);

}



/**
@@ -3550,15 +3587,7 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev, 
	radeon_ring_write(ring, fence->seq);

	radeon_ring_write(ring, 0);

	/* HDP flush */

	/* We should be using the new WAIT_REG_MEM special op packet here

	 * but it causes the CP to hang

	 */

	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |

				 WRITE_DATA_DST_SEL(0)));

	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 0);

	cik_hdp_flush_cp_ring_emit(rdev, fence->ring);

}



bool cik_semaphore_ring_emit(struct radeon_device *rdev,
@@ -3566,8 +3595,6 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev, 
			     struct radeon_semaphore *semaphore,

			     bool emit_wait)

{

/* TODO: figure out why semaphore cause lockups */

#if 0

	uint64_t addr = semaphore->gpu_addr;

	unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
@@ -3576,9 +3603,6 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev, 
	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);



	return true;

#else

	return false;

#endif

}



/**
@@ -5329,20 +5353,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) 
				WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);



	/* TC cache setup ??? */

	WREG32(TC_CFG_L1_LOAD_POLICY0, 0);

	WREG32(TC_CFG_L1_LOAD_POLICY1, 0);

	WREG32(TC_CFG_L1_STORE_POLICY, 0);



	WREG32(TC_CFG_L2_LOAD_POLICY0, 0);

	WREG32(TC_CFG_L2_LOAD_POLICY1, 0);

	WREG32(TC_CFG_L2_STORE_POLICY0, 0);

	WREG32(TC_CFG_L2_STORE_POLICY1, 0);

	WREG32(TC_CFG_L2_ATOMIC_POLICY, 0);



	WREG32(TC_CFG_L1_VOLATILE, 0);

	WREG32(TC_CFG_L2_VOLATILE, 0);



	if (rdev->family == CHIP_KAVERI) {

		u32 tmp = RREG32(CHUB_CONTROL);

		tmp &= ~BYPASS_VM;
@@ -5558,16 +5568,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 
	radeon_ring_write(ring, VMID(0));



	/* HDP flush */

	/* We should be using the WAIT_REG_MEM packet here like in

	 * cik_fence_ring_emit(), but it causes the CP to hang in this

	 * context...

	 */

	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |

				 WRITE_DATA_DST_SEL(0)));

	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 0);

	cik_hdp_flush_cp_ring_emit(rdev, ridx);



	/* bits 0-15 are the VM contexts0-15 */

	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/cik_sdma.c

+31 −12
Original line number Diff line number Diff line
@@ -156,6 +156,35 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev, 


}



/**

 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring

 *

 * @rdev: radeon_device pointer

 * @ridx: radeon ring index

 *

 * Emit an hdp flush packet on the requested DMA ring.

 */

static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,

					 int ridx)

{

	struct radeon_ring *ring = &rdev->ring[ridx];

	u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |

			  SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */

	u32 ref_and_mask;



	if (ridx == R600_RING_TYPE_DMA_INDEX)

		ref_and_mask = SDMA0;

	else

		ref_and_mask = SDMA1;



	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));

	radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);

	radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);

	radeon_ring_write(ring, ref_and_mask); /* reference */

	radeon_ring_write(ring, ref_and_mask); /* mask */

	radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */

}



/**

 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring

 *
@@ -180,12 +209,7 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 
	/* generate an interrupt */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));

	/* flush HDP */

	/* We should be using the new POLL_REG_MEM special op packet here

	 * but it causes sDMA to hang sometimes

	 */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

	radeon_ring_write(ring, 0);

	cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);

}



/**
@@ -816,12 +840,7 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm 
	radeon_ring_write(ring, VMID(0));



	/* flush HDP */

	/* We should be using the new POLL_REG_MEM special op packet here

	 * but it causes sDMA to hang sometimes

	 */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

	radeon_ring_write(ring, 0);

	cik_sdma_hdp_flush_ring_emit(rdev, ridx);



	/* flush TLB */

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/ni.c

+7 −9
Original line number Diff line number Diff line
@@ -1331,13 +1331,12 @@ void cayman_fence_ring_emit(struct radeon_device *rdev, 
{

	struct radeon_ring *ring = &rdev->ring[fence->ring];

	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;

	u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |

		PACKET3_SH_ACTION_ENA;



	/* flush read cache over gart for this vmid */

	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

	radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

	radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);

	radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);

	radeon_ring_write(ring, 0xFFFFFFFF);

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 10); /* poll interval */
@@ -1353,6 +1352,8 @@ void cayman_fence_ring_emit(struct radeon_device *rdev, 
void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)

{

	struct radeon_ring *ring = &rdev->ring[ib->ring];

	u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |

		PACKET3_SH_ACTION_ENA;



	/* set to DX10/11 mode */

	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
@@ -1377,14 +1378,11 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 
			  (ib->vm ? (ib->vm->id << 24) : 0));



	/* flush read cache over gart for this vmid */

	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

	radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);

	radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);

	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

	radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);

	radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);

	radeon_ring_write(ring, 0xFFFFFFFF);

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 10); /* poll interval */

	radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */

}



static void cayman_cp_enable(struct radeon_device *rdev, bool enable)

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