Commit 8c933eab authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlxsw-Make-port-split-code-more-generic' 



Ido Schimmel says:

====================
mlxsw: Make port split code more generic

Jiri says:

Currently, we assume some limitations and constant values which are not
applicable for Spectrum-3 which has 8 lanes ports (instead of previous 4
lanes).

This patch does 2 things:

1) Generalizes the code to not use constants so it can work for 4, 8 and
   possibly 16 lanes.

2) Enforces some assumptions we had in the code but did not check.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d74361dc 973b7fdb

drivers/net/ethernet/mellanox/mlxsw/core.c

+29 −0
Original line number Diff line number Diff line
@@ -2017,6 +2017,35 @@ mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 
}

EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get);



int mlxsw_core_module_max_width(struct mlxsw_core *mlxsw_core, u8 module)

{

	enum mlxsw_reg_pmtm_module_type module_type;

	char pmtm_pl[MLXSW_REG_PMTM_LEN];

	int err;



	mlxsw_reg_pmtm_pack(pmtm_pl, module);

	err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtm), pmtm_pl);

	if (err)

		return err;

	mlxsw_reg_pmtm_unpack(pmtm_pl, &module_type);



	/* Here we need to get the module width according to the module type. */



	switch (module_type) {

	case MLXSW_REG_PMTM_MODULE_TYPE_BP_4X: /* fall through */

	case MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP:

		return 4;

	case MLXSW_REG_PMTM_MODULE_TYPE_BP_2X:

		return 2;

	case MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP: /* fall through */

	case MLXSW_REG_PMTM_MODULE_TYPE_BP_1X:

		return 1;

	default:

		return -EINVAL;

	}

}

EXPORT_SYMBOL(mlxsw_core_module_max_width);



static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core,

				    const char *buf, size_t size)

{

drivers/net/ethernet/mellanox/mlxsw/core.h

+1 −0
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core, 
struct devlink_port *

mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core,

				 u8 local_port);

int mlxsw_core_module_max_width(struct mlxsw_core *mlxsw_core, u8 module);



int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay);

bool mlxsw_core_schedule_work(struct work_struct *work);

drivers/net/ethernet/mellanox/mlxsw/port.h

+0 −2
Original line number Diff line number Diff line
@@ -24,8 +24,6 @@ 


#define MLXSW_PORT_DONT_CARE		0xFF



#define MLXSW_PORT_MODULE_MAX_WIDTH	4



enum mlxsw_port_admin_status {

	MLXSW_PORT_ADMIN_STATUS_UP = 1,

	MLXSW_PORT_ADMIN_STATUS_DOWN = 2,

drivers/net/ethernet/mellanox/mlxsw/reg.h

+53 −2
Original line number Diff line number Diff line
@@ -3969,6 +3969,7 @@ MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 
 * 1 - Lane 0 is used.

 * 2 - Lanes 0 and 1 are used.

 * 4 - Lanes 0, 1, 2 and 3 are used.

 * 8 - Lanes 0-7 are used.

 * Access: RW

 */

MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
@@ -3983,14 +3984,14 @@ MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 
 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);

MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);



/* reg_pmlp_rx_lane

 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is

 * equal to Tx lane.

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);

MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);



static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)

{
@@ -5374,6 +5375,55 @@ static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 
				 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);

}



/* PMTM - Port Module Type Mapping Register

 * ----------------------------------------

 * The PMTM allows query or configuration of module types.

 */

#define MLXSW_REG_PMTM_ID 0x5067

#define MLXSW_REG_PMTM_LEN 0x10



MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);



/* reg_pmtm_module

 * Module number.

 * Access: Index

 */

MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);



enum mlxsw_reg_pmtm_module_type {

	/* Backplane with 4 lanes */

	MLXSW_REG_PMTM_MODULE_TYPE_BP_4X,

	/* QSFP */

	MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP,

	/* SFP */

	MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP,

	/* Backplane with single lane */

	MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4,

	/* Backplane with two lane */

	MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8,

	/* Chip2Chip */

	MLXSW_REG_PMTM_MODULE_TYPE_C2C = 10,

};



/* reg_pmtm_module_type

 * Module type.

 * Access: RW

 */

MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4);



static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module)

{

	MLXSW_REG_ZERO(pmtm, payload);

	mlxsw_reg_pmtm_module_set(payload, module);

}



static inline void

mlxsw_reg_pmtm_unpack(char *payload,

		      enum mlxsw_reg_pmtm_module_type *module_type)

{

	*module_type = mlxsw_reg_pmtm_module_type_get(payload);

}



/* HTGT - Host Trap Group Table

 * ----------------------------

 * Configures the properties for forwarding to CPU.
@@ -10544,6 +10594,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 
	MLXSW_REG(pbmc),

	MLXSW_REG(pspa),

	MLXSW_REG(pplr),

	MLXSW_REG(pmtm),

	MLXSW_REG(htgt),

	MLXSW_REG(hpkt),

	MLXSW_REG(rgcr),

drivers/net/ethernet/mellanox/mlxsw/resources.h

+2 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ enum mlxsw_res_id { 
	MLXSW_RES_ID_MAX_LAG_MEMBERS,

	MLXSW_RES_ID_LOCAL_PORTS_IN_1X,

	MLXSW_RES_ID_LOCAL_PORTS_IN_2X,

	MLXSW_RES_ID_LOCAL_PORTS_IN_4X,

	MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,

	MLXSW_RES_ID_CELL_SIZE,

	MLXSW_RES_ID_MAX_HEADROOM_SIZE,
@@ -82,6 +83,7 @@ static u16 mlxsw_res_ids[] = { 
	[MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,

	[MLXSW_RES_ID_LOCAL_PORTS_IN_1X] = 0x2610,

	[MLXSW_RES_ID_LOCAL_PORTS_IN_2X] = 0x2611,

	[MLXSW_RES_ID_LOCAL_PORTS_IN_4X] = 0x2612,

	[MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805,	/* Bytes */

	[MLXSW_RES_ID_CELL_SIZE] = 0x2803,	/* Bytes */

	[MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811,	/* Bytes */

CRA Git | Maintained and supported by SUSTech CRA and CCSE