Commit 8c7634c0 authored by Peter Crosthwaite's avatar Peter Crosthwaite Committed by Michal Simek
Browse files

arm: dts: zynq: Move crystal freq. to board level 



The fact that all supported boards use the same 33MHz crystal is a
co-incidence. The Zynq PS support a range of crystal freqs so the
hardcoded setting should be removed from the dtsi. Re-implement it
on the board level.

This prepares support for Zynq boards with different crystal
frequencies (e.g. the Digilent ZYBO).

Acked-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: default avatarPeter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent d86e3104

arch/arm/boot/dts/zynq-7000.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -244,7 +244,6 @@ 
			clkc: clkc@100 {

				#clock-cells = <1>;

				compatible = "xlnx,ps7-clkc";

				ps-clk-frequency = <33333333>;

				fclk-enable = <0>;

				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",

						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",

arch/arm/boot/dts/zynq-parallella.dts

+4 −0
Original line number Diff line number Diff line
@@ -34,6 +34,10 @@ 
	};

};



&clkc {

	ps-clk-frequency = <33333333>;

};



&gem0 {

	status = "okay";

	phy-mode = "rgmii-id";

arch/arm/boot/dts/zynq-zc702.dts

+4 −0
Original line number Diff line number Diff line
@@ -42,6 +42,10 @@ 
	status = "okay";

};



&clkc {

	ps-clk-frequency = <33333333>;

};



&gem0 {

	status = "okay";

	phy-mode = "rgmii-id";

arch/arm/boot/dts/zynq-zc706.dts

+4 −0
Original line number Diff line number Diff line
@@ -29,6 +29,10 @@ 


};



&clkc {

	ps-clk-frequency = <33333333>;

};



&gem0 {

	status = "okay";

	phy-mode = "rgmii-id";

arch/arm/boot/dts/zynq-zed.dts

+4 −0
Original line number Diff line number Diff line
@@ -29,6 +29,10 @@ 


};



&clkc {

	ps-clk-frequency = <33333333>;

};



&gem0 {

	status = "okay";

	phy-mode = "rgmii-id";

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