Commit 8c6bb62f authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Vinod Koul
Browse files

dmaengine: ti: k3 PSI-L remote endpoint configuration 



In K3 architecture the DMA operates within threads. One end of the thread
is UDMAP, the other is on the peripheral side.

The UDMAP channel configuration depends on the needs of the remote
endpoint and it can be differ from peripheral to peripheral.

This patch adds database for am654 and j721e and small API to fetch the
PSI-L endpoint configuration from the database which should only used by
the DMA driver(s).

Another API is added for native peripherals to give possibility to pass new
configuration for the threads they are using, which is needed to be able to
handle changes caused by different firmware loaded for the peripheral for
example.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: default avatarKeerthy <j-keerthy@ti.com>
Reviewed-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20191223110458.30766-9-peter.ujfalusi@ti.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 69bafc31

drivers/dma/ti/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -34,5 +34,8 @@ config DMA_OMAP 
	  Enable support for the TI sDMA (System DMA or DMA4) controller. This

	  DMA engine is found on OMAP and DRA7xx parts.



config TI_K3_PSIL

	bool



config TI_DMA_CROSSBAR

	bool

drivers/dma/ti/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -2,4 +2,5 @@ 
obj-$(CONFIG_TI_CPPI41) += cppi41.o

obj-$(CONFIG_TI_EDMA) += edma.o

obj-$(CONFIG_DMA_OMAP) += omap-dma.o

obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o k3-psil-am654.o k3-psil-j721e.o

obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o

drivers/dma/ti/k3-psil-am654.c

0 → 100644
+175 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com

 *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>

 */



#include <linux/kernel.h>



#include "k3-psil-priv.h"



#define PSIL_PDMA_XY_TR(x)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_PDMA_XY,	\

		},					\

	}



#define PSIL_PDMA_XY_PKT(x)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_PDMA_XY,	\

			.pkt_mode = 1,			\

		},					\

	}



#define PSIL_ETHERNET(x)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_NATIVE,	\

			.pkt_mode = 1,			\

			.needs_epib = 1,		\

			.psd_size = 16,			\

		},					\

	}



#define PSIL_SA2UL(x, tx)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_NATIVE,	\

			.pkt_mode = 1,			\

			.needs_epib = 1,		\

			.psd_size = 64,			\

			.notdpkt = tx,			\

		},					\

	}



/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */

struct psil_ep am654_src_ep_map[] = {

	/* SA2UL */

	PSIL_SA2UL(0x4000, 0),

	PSIL_SA2UL(0x4001, 0),

	PSIL_SA2UL(0x4002, 0),

	PSIL_SA2UL(0x4003, 0),

	/* PRU_ICSSG0 */

	PSIL_ETHERNET(0x4100),

	PSIL_ETHERNET(0x4101),

	PSIL_ETHERNET(0x4102),

	PSIL_ETHERNET(0x4103),

	/* PRU_ICSSG1 */

	PSIL_ETHERNET(0x4200),

	PSIL_ETHERNET(0x4201),

	PSIL_ETHERNET(0x4202),

	PSIL_ETHERNET(0x4203),

	/* PRU_ICSSG2 */

	PSIL_ETHERNET(0x4300),

	PSIL_ETHERNET(0x4301),

	PSIL_ETHERNET(0x4302),

	PSIL_ETHERNET(0x4303),

	/* PDMA0 - McASPs */

	PSIL_PDMA_XY_TR(0x4400),

	PSIL_PDMA_XY_TR(0x4401),

	PSIL_PDMA_XY_TR(0x4402),

	/* PDMA1 - SPI0-4 */

	PSIL_PDMA_XY_PKT(0x4500),

	PSIL_PDMA_XY_PKT(0x4501),

	PSIL_PDMA_XY_PKT(0x4502),

	PSIL_PDMA_XY_PKT(0x4503),

	PSIL_PDMA_XY_PKT(0x4504),

	PSIL_PDMA_XY_PKT(0x4505),

	PSIL_PDMA_XY_PKT(0x4506),

	PSIL_PDMA_XY_PKT(0x4507),

	PSIL_PDMA_XY_PKT(0x4508),

	PSIL_PDMA_XY_PKT(0x4509),

	PSIL_PDMA_XY_PKT(0x450a),

	PSIL_PDMA_XY_PKT(0x450b),

	PSIL_PDMA_XY_PKT(0x450c),

	PSIL_PDMA_XY_PKT(0x450d),

	PSIL_PDMA_XY_PKT(0x450e),

	PSIL_PDMA_XY_PKT(0x450f),

	PSIL_PDMA_XY_PKT(0x4510),

	PSIL_PDMA_XY_PKT(0x4511),

	PSIL_PDMA_XY_PKT(0x4512),

	PSIL_PDMA_XY_PKT(0x4513),

	/* PDMA1 - USART0-2 */

	PSIL_PDMA_XY_PKT(0x4514),

	PSIL_PDMA_XY_PKT(0x4515),

	PSIL_PDMA_XY_PKT(0x4516),

	/* CPSW0 */

	PSIL_ETHERNET(0x7000),

	/* MCU_PDMA0 - ADCs */

	PSIL_PDMA_XY_TR(0x7100),

	PSIL_PDMA_XY_TR(0x7101),

	PSIL_PDMA_XY_TR(0x7102),

	PSIL_PDMA_XY_TR(0x7103),

	/* MCU_PDMA1 - MCU_SPI0-2 */

	PSIL_PDMA_XY_PKT(0x7200),

	PSIL_PDMA_XY_PKT(0x7201),

	PSIL_PDMA_XY_PKT(0x7202),

	PSIL_PDMA_XY_PKT(0x7203),

	PSIL_PDMA_XY_PKT(0x7204),

	PSIL_PDMA_XY_PKT(0x7205),

	PSIL_PDMA_XY_PKT(0x7206),

	PSIL_PDMA_XY_PKT(0x7207),

	PSIL_PDMA_XY_PKT(0x7208),

	PSIL_PDMA_XY_PKT(0x7209),

	PSIL_PDMA_XY_PKT(0x720a),

	PSIL_PDMA_XY_PKT(0x720b),

	/* MCU_PDMA1 - MCU_USART0 */

	PSIL_PDMA_XY_PKT(0x7212),

};



/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */

struct psil_ep am654_dst_ep_map[] = {

	/* SA2UL */

	PSIL_SA2UL(0xc000, 1),

	PSIL_SA2UL(0xc001, 1),

	/* PRU_ICSSG0 */

	PSIL_ETHERNET(0xc100),

	PSIL_ETHERNET(0xc101),

	PSIL_ETHERNET(0xc102),

	PSIL_ETHERNET(0xc103),

	PSIL_ETHERNET(0xc104),

	PSIL_ETHERNET(0xc105),

	PSIL_ETHERNET(0xc106),

	PSIL_ETHERNET(0xc107),

	/* PRU_ICSSG1 */

	PSIL_ETHERNET(0xc200),

	PSIL_ETHERNET(0xc201),

	PSIL_ETHERNET(0xc202),

	PSIL_ETHERNET(0xc203),

	PSIL_ETHERNET(0xc204),

	PSIL_ETHERNET(0xc205),

	PSIL_ETHERNET(0xc206),

	PSIL_ETHERNET(0xc207),

	/* PRU_ICSSG2 */

	PSIL_ETHERNET(0xc300),

	PSIL_ETHERNET(0xc301),

	PSIL_ETHERNET(0xc302),

	PSIL_ETHERNET(0xc303),

	PSIL_ETHERNET(0xc304),

	PSIL_ETHERNET(0xc305),

	PSIL_ETHERNET(0xc306),

	PSIL_ETHERNET(0xc307),

	/* CPSW0 */

	PSIL_ETHERNET(0xf000),

	PSIL_ETHERNET(0xf001),

	PSIL_ETHERNET(0xf002),

	PSIL_ETHERNET(0xf003),

	PSIL_ETHERNET(0xf004),

	PSIL_ETHERNET(0xf005),

	PSIL_ETHERNET(0xf006),

	PSIL_ETHERNET(0xf007),

};



struct psil_ep_map am654_ep_map = {

	.name = "am654",

	.src = am654_src_ep_map,

	.src_count = ARRAY_SIZE(am654_src_ep_map),

	.dst = am654_dst_ep_map,

	.dst_count = ARRAY_SIZE(am654_dst_ep_map),

};

drivers/dma/ti/k3-psil-j721e.c

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Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com

 *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>

 */



#include <linux/kernel.h>



#include "k3-psil-priv.h"



#define PSIL_PDMA_XY_TR(x)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_PDMA_XY,	\

		},					\

	}



#define PSIL_PDMA_XY_PKT(x)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_PDMA_XY,	\

			.pkt_mode = 1,			\

		},					\

	}



#define PSIL_PDMA_MCASP(x)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_PDMA_XY,	\

			.pdma_acc32 = 1,		\

			.pdma_burst = 1,		\

		},					\

	}



#define PSIL_ETHERNET(x)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_NATIVE,	\

			.pkt_mode = 1,			\

			.needs_epib = 1,		\

			.psd_size = 16,			\

		},					\

	}



#define PSIL_SA2UL(x, tx)				\

	{						\

		.thread_id = x,				\

		.ep_config = {				\

			.ep_type = PSIL_EP_NATIVE,	\

			.pkt_mode = 1,			\

			.needs_epib = 1,		\

			.psd_size = 64,			\

			.notdpkt = tx,			\

		},					\

	}



/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */

struct psil_ep j721e_src_ep_map[] = {

	/* SA2UL */

	PSIL_SA2UL(0x4000, 0),

	PSIL_SA2UL(0x4001, 0),

	PSIL_SA2UL(0x4002, 0),

	PSIL_SA2UL(0x4003, 0),

	/* PRU_ICSSG0 */

	PSIL_ETHERNET(0x4100),

	PSIL_ETHERNET(0x4101),

	PSIL_ETHERNET(0x4102),

	PSIL_ETHERNET(0x4103),

	/* PRU_ICSSG1 */

	PSIL_ETHERNET(0x4200),

	PSIL_ETHERNET(0x4201),

	PSIL_ETHERNET(0x4202),

	PSIL_ETHERNET(0x4203),

	/* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */

	PSIL_PDMA_MCASP(0x4400),

	PSIL_PDMA_MCASP(0x4401),

	PSIL_PDMA_MCASP(0x4402),

	/* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */

	PSIL_PDMA_MCASP(0x4500),

	PSIL_PDMA_MCASP(0x4501),

	PSIL_PDMA_MCASP(0x4502),

	PSIL_PDMA_MCASP(0x4503),

	PSIL_PDMA_MCASP(0x4504),

	PSIL_PDMA_MCASP(0x4505),

	PSIL_PDMA_MCASP(0x4506),

	PSIL_PDMA_MCASP(0x4507),

	PSIL_PDMA_MCASP(0x4508),

	/* PDMA8 (PDMA_MISC_G0) - SPI0-1 */

	PSIL_PDMA_XY_PKT(0x4600),

	PSIL_PDMA_XY_PKT(0x4601),

	PSIL_PDMA_XY_PKT(0x4602),

	PSIL_PDMA_XY_PKT(0x4603),

	PSIL_PDMA_XY_PKT(0x4604),

	PSIL_PDMA_XY_PKT(0x4605),

	PSIL_PDMA_XY_PKT(0x4606),

	PSIL_PDMA_XY_PKT(0x4607),

	/* PDMA9 (PDMA_MISC_G1) - SPI2-3 */

	PSIL_PDMA_XY_PKT(0x460c),

	PSIL_PDMA_XY_PKT(0x460d),

	PSIL_PDMA_XY_PKT(0x460e),

	PSIL_PDMA_XY_PKT(0x460f),

	PSIL_PDMA_XY_PKT(0x4610),

	PSIL_PDMA_XY_PKT(0x4611),

	PSIL_PDMA_XY_PKT(0x4612),

	PSIL_PDMA_XY_PKT(0x4613),

	/* PDMA10 (PDMA_MISC_G2) - SPI4-5 */

	PSIL_PDMA_XY_PKT(0x4618),

	PSIL_PDMA_XY_PKT(0x4619),

	PSIL_PDMA_XY_PKT(0x461a),

	PSIL_PDMA_XY_PKT(0x461b),

	PSIL_PDMA_XY_PKT(0x461c),

	PSIL_PDMA_XY_PKT(0x461d),

	PSIL_PDMA_XY_PKT(0x461e),

	PSIL_PDMA_XY_PKT(0x461f),

	/* PDMA11 (PDMA_MISC_G3) */

	PSIL_PDMA_XY_PKT(0x4624),

	PSIL_PDMA_XY_PKT(0x4625),

	PSIL_PDMA_XY_PKT(0x4626),

	PSIL_PDMA_XY_PKT(0x4627),

	PSIL_PDMA_XY_PKT(0x4628),

	PSIL_PDMA_XY_PKT(0x4629),

	PSIL_PDMA_XY_PKT(0x4630),

	PSIL_PDMA_XY_PKT(0x463a),

	/* PDMA13 (PDMA_USART_G0) - UART0-1 */

	PSIL_PDMA_XY_PKT(0x4700),

	PSIL_PDMA_XY_PKT(0x4701),

	/* PDMA14 (PDMA_USART_G1) - UART2-3 */

	PSIL_PDMA_XY_PKT(0x4702),

	PSIL_PDMA_XY_PKT(0x4703),

	/* PDMA15 (PDMA_USART_G2) - UART4-9 */

	PSIL_PDMA_XY_PKT(0x4704),

	PSIL_PDMA_XY_PKT(0x4705),

	PSIL_PDMA_XY_PKT(0x4706),

	PSIL_PDMA_XY_PKT(0x4707),

	PSIL_PDMA_XY_PKT(0x4708),

	PSIL_PDMA_XY_PKT(0x4709),

	/* CPSW9 */

	PSIL_ETHERNET(0x4a00),

	/* CPSW0 */

	PSIL_ETHERNET(0x7000),

	/* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */

	PSIL_PDMA_XY_PKT(0x7100),

	PSIL_PDMA_XY_PKT(0x7101),

	PSIL_PDMA_XY_PKT(0x7102),

	PSIL_PDMA_XY_PKT(0x7103),

	/* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */

	PSIL_PDMA_XY_PKT(0x7200),

	PSIL_PDMA_XY_PKT(0x7201),

	PSIL_PDMA_XY_PKT(0x7202),

	PSIL_PDMA_XY_PKT(0x7203),

	PSIL_PDMA_XY_PKT(0x7204),

	PSIL_PDMA_XY_PKT(0x7205),

	PSIL_PDMA_XY_PKT(0x7206),

	PSIL_PDMA_XY_PKT(0x7207),

	/* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */

	PSIL_PDMA_XY_PKT(0x7300),

	/* MCU_PDMA_ADC - ADC0-1 */

	PSIL_PDMA_XY_TR(0x7400),

	PSIL_PDMA_XY_TR(0x7401),

	PSIL_PDMA_XY_TR(0x7402),

	PSIL_PDMA_XY_TR(0x7403),

	/* SA2UL */

	PSIL_SA2UL(0x7500, 0),

	PSIL_SA2UL(0x7501, 0),

};



/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */

struct psil_ep j721e_dst_ep_map[] = {

	/* SA2UL */

	PSIL_SA2UL(0xc000, 1),

	PSIL_SA2UL(0xc001, 1),

	/* PRU_ICSSG0 */

	PSIL_ETHERNET(0xc100),

	PSIL_ETHERNET(0xc101),

	PSIL_ETHERNET(0xc102),

	PSIL_ETHERNET(0xc103),

	PSIL_ETHERNET(0xc104),

	PSIL_ETHERNET(0xc105),

	PSIL_ETHERNET(0xc106),

	PSIL_ETHERNET(0xc107),

	/* PRU_ICSSG1 */

	PSIL_ETHERNET(0xc200),

	PSIL_ETHERNET(0xc201),

	PSIL_ETHERNET(0xc202),

	PSIL_ETHERNET(0xc203),

	PSIL_ETHERNET(0xc204),

	PSIL_ETHERNET(0xc205),

	PSIL_ETHERNET(0xc206),

	PSIL_ETHERNET(0xc207),

	/* CPSW9 */

	PSIL_ETHERNET(0xca00),

	PSIL_ETHERNET(0xca01),

	PSIL_ETHERNET(0xca02),

	PSIL_ETHERNET(0xca03),

	PSIL_ETHERNET(0xca04),

	PSIL_ETHERNET(0xca05),

	PSIL_ETHERNET(0xca06),

	PSIL_ETHERNET(0xca07),

	/* CPSW0 */

	PSIL_ETHERNET(0xf000),

	PSIL_ETHERNET(0xf001),

	PSIL_ETHERNET(0xf002),

	PSIL_ETHERNET(0xf003),

	PSIL_ETHERNET(0xf004),

	PSIL_ETHERNET(0xf005),

	PSIL_ETHERNET(0xf006),

	PSIL_ETHERNET(0xf007),

	/* SA2UL */

	PSIL_SA2UL(0xf500, 1),

};



struct psil_ep_map j721e_ep_map = {

	.name = "j721e",

	.src = j721e_src_ep_map,

	.src_count = ARRAY_SIZE(j721e_src_ep_map),

	.dst = j721e_dst_ep_map,

	.dst_count = ARRAY_SIZE(j721e_dst_ep_map),

};

drivers/dma/ti/k3-psil-priv.h

0 → 100644
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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com

 */



#ifndef K3_PSIL_PRIV_H_

#define K3_PSIL_PRIV_H_



#include <linux/dma/k3-psil.h>



struct psil_ep {

	u32 thread_id;

	struct psil_endpoint_config ep_config;

};



/**

 * struct psil_ep_map - PSI-L thread ID configuration maps

 * @name:	Name of the map, set it to the name of the SoC

 * @src:	Array of source PSI-L thread configurations

 * @src_count:	Number of entries in the src array

 * @dst:	Array of destination PSI-L thread configurations

 * @dst_count:	Number of entries in the dst array

 *

 * In case of symmetric configuration for a matching src/dst thread (for example

 * 0x4400 and 0xc400) only the src configuration can be present. If no dst

 * configuration found the code will look for (dst_thread_id & ~0x8000) to find

 * the symmetric match.

 */

struct psil_ep_map {

	char *name;

	struct psil_ep	*src;

	int src_count;

	struct psil_ep	*dst;

	int dst_count;

};



struct psil_endpoint_config *psil_get_ep_config(u32 thread_id);



#endif /* K3_PSIL_PRIV_H_ */

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