Commit 8c31459d authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
Browse files

powerpc/perf: Cleanup cache_sel bits comment 



Update the raw event code comment in power9-pmu.c with respect to
"cache" bits, since power9 MMCRC does not support these.

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 333804dc

arch/powerpc/perf/power9-pmu.c

+2 −10
Original line number Diff line number Diff line
@@ -63,14 +63,6 @@ 
 *	MMCRA[9:11] = thresh_cmp[0:2]

 *	MMCRA[12:18] = thresh_cmp[3:9]

 *

 * if unit == 6 or unit == 7

 *	MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)

 * else if unit == 8 or unit == 9:

 *	if cache_sel[0] == 0: # L3 bank

 *		MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)

 *	else if cache_sel[0] == 1:

 *		MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)

 * else if cache_sel[1]: # L1 event

 * MMCR1[16] = cache_sel[2]

 * MMCR1[17] = cache_sel[3]

 *

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