Commit 8c310557 authored by Flavio Suligoi's avatar Flavio Suligoi Committed by Rob Herring
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doc: devicetree: bindings: fix spelling mistake

parent d0793c3c
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@@ -12,7 +12,7 @@ Required properties for the top level node:
   Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt. Should be 2. The first cell defines the interrupt number,
   the second encodes the triger flags encoded as described in
   the second encodes the trigger flags encoded as described in
   Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- compatible:
  - "mediatek,mt7621-gpio" for Mediatek controllers
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@@ -10,7 +10,7 @@ Interrupt number definition:
 16-31  : private  irq, and we use 16 as the co-processor timer.
 31-1024: common irq for soc ip.

Interrupt triger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
 IRQ_TYPE_LEVEL_HIGH (default)
 IRQ_TYPE_LEVEL_LOW
 IRQ_TYPE_EDGE_RISING
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@@ -8,7 +8,7 @@ regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
 - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
 - PTIM_TSR  "cr<1, 14>" Interrupt cleanup status reg.
 - PTIM_CCVR "cr<3, 14>" Current counter value reg.
 - PTIM_LVR  "cr<6, 14>" Window value reg to triger next event.
 - PTIM_LVR  "cr<6, 14>" Window value reg to trigger next event.

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timer node bindings definition