Commit 8c2dcbd2 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: Add helper to decode register from instruction 



Add a helper to extract the register field from a given
instruction.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent c9ee0f98

arch/arm64/include/asm/insn.h

+2 −0
Original line number Diff line number Diff line
@@ -332,6 +332,8 @@ bool aarch64_insn_is_branch(u32 insn); 
u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);

u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,

				  u32 insn, u64 imm);

u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,

					 u32 insn);

u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,

				enum aarch64_insn_branch_type type);

u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,

arch/arm64/kernel/insn.c

+29 −0
Original line number Diff line number Diff line
@@ -417,6 +417,35 @@ u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, 
	return insn;

}



u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,

					u32 insn)

{

	int shift;



	switch (type) {

	case AARCH64_INSN_REGTYPE_RT:

	case AARCH64_INSN_REGTYPE_RD:

		shift = 0;

		break;

	case AARCH64_INSN_REGTYPE_RN:

		shift = 5;

		break;

	case AARCH64_INSN_REGTYPE_RT2:

	case AARCH64_INSN_REGTYPE_RA:

		shift = 10;

		break;

	case AARCH64_INSN_REGTYPE_RM:

		shift = 16;

		break;

	default:

		pr_err("%s: unknown register type encoding %d\n", __func__,

		       type);

		return 0;

	}



	return (insn >> shift) & GENMASK(4, 0);

}



static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,

					u32 insn,

					enum aarch64_insn_register reg)

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