Commit 8c17bbf6 authored by Shuah Khan's avatar Shuah Khan Committed by Joerg Roedel
Browse files

iommu/amd: Fix IOMMU perf counter clobbering during init 



init_iommu_perf_ctr() clobbers the register when it checks write access
to IOMMU perf counters and fails to restore when they are writable.

Add save and restore to fix it.

Signed-off-by: default avatarShuah Khan <skhan@linuxfoundation.org>
Fixes: 30861ddc ("perf/x86/amd: Add IOMMU Performance Counter resource management")
Reviewed-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Tested-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent bf708cfb

drivers/iommu/amd_iommu_init.c

+18 −6
Original line number Diff line number Diff line
@@ -1655,27 +1655,39 @@ static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 
static void init_iommu_perf_ctr(struct amd_iommu *iommu)

{

	struct pci_dev *pdev = iommu->dev;

	u64 val = 0xabcd, val2 = 0;

	u64 val = 0xabcd, val2 = 0, save_reg = 0;



	if (!iommu_feature(iommu, FEATURE_PC))

		return;



	amd_iommu_pc_present = true;



	/* save the value to restore, if writable */

	if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false))

		goto pc_false;



	/* Check if the performance counters can be written to */

	if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||

	    (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||

	    (val != val2)) {

		pci_err(pdev, "Unable to write to IOMMU perf counter.\n");

		amd_iommu_pc_present = false;

		return;

	}

	    (val != val2))

		goto pc_false;



	/* restore */

	if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true))

		goto pc_false;



	pci_info(pdev, "IOMMU performance counters supported\n");



	val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);

	iommu->max_banks = (u8) ((val >> 12) & 0x3f);

	iommu->max_counters = (u8) ((val >> 7) & 0xf);



	return;



pc_false:

	pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n");

	amd_iommu_pc_present = false;

	return;

}



static ssize_t amd_iommu_show_cap(struct device *dev,

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