drm/amdgpu: Add Fine Grain Clock Gating for GFX10 (8c11024c) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+45 −0

Original line number	Diff line number	Diff line
		@@ -7658,12 +7658,50 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
		}
		}

		static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
		bool enable)
		{
		uint32_t def, data;

		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
		/* unset FGCG override */
		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
		/* update FGCG override bits */
		if (def != data)
		WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
		/* unset RLC SRAM CLK GATER override */
		data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
		/* update RLC SRAM CLK GATER override bits */
		if (def != data)
		WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
		} else {
		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
		/* reset FGCG bits */
		data \|= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
		/* disable FGCG*/
		if (def != data)
		WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);

		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
		/* reset RLC SRAM CLK GATER bits */
		data \|= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
		/* disable RLC SRAM CLK*/
		if (def != data)
		WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
		}
		}

		static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
		bool enable)
		{
		amdgpu_gfx_rlc_enter_safe_mode(adev);

		if (enable) {
		/* enable FGCG firstly*/
		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
		/* CGCG/CGLS should be enabled after MGCG/MGLS
		* === MGCG + MGLS ===
		*/
		@@ -7681,6 +7719,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
		gfx_v10_0_update_3d_clock_gating(adev, enable);
		/* === MGCG + MGLS === */
		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
		/* disable fgcg at last*/
		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
		}

		if (adev->cg_flags &
		@@ -7849,6 +7889,11 @@ static void gfx_v10_0_get_clockgating_state(void handle, u32 flags)
		struct amdgpu_device adev = (struct amdgpu_device )handle;
		int data;

		/* AMD_CG_SUPPORT_GFX_FGCG */
		data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
		if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
		*flags \|= AMD_CG_SUPPORT_GFX_FGCG;

		/* AMD_CG_SUPPORT_GFX_MGCG */
		data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
		if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))

Admin message