Commit 8bff8399 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "Another round of MIPS fixes for 4.2.

  Things are looking quite decent at this stage but the recent work on
  the FPU support took its toll:

   - fix an incorrect overly restrictive ifdef

   - select O32 64-bit FP support for O32 binary compatibility

   - remove workarounds for Sibyte SB1250 Pass1 parts.  There are rare
     fixing the workarounds is not worth the effort.

   - patch up an outdated and now incorrect comment"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6 CPU
  MIPS: SB1: Remove support for Pass 1 parts.
  MIPS: Require O32 FP64 support for MIPS64 with O32 compat
  MIPS: asm-offset.c: Patch up various comments refering to the old filename.
parents ff72bf7a fcc53b5f

arch/mips/Kconfig

+1 −5
Original line number Diff line number Diff line
@@ -1427,6 +1427,7 @@ config CPU_MIPS64_R6 
	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_MSA

	select GENERIC_CSUM

	select MIPS_O32_FP64_SUPPORT if MIPS32_O32

	help

	  Choose this option to build a kernel for release 6 or later of the

	  MIPS64 architecture.  New MIPS processors, starting with the Warrior
@@ -2262,11 +2263,6 @@ config MIPS_CM 
config MIPS_CPC

	bool



config SB1_PASS_1_WORKAROUNDS

	bool

	depends on CPU_SB1_PASS_1

	default y



config SB1_PASS_2_WORKAROUNDS

	bool

	depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)

arch/mips/Makefile

+0 −7
Original line number Diff line number Diff line
@@ -181,13 +181,6 @@ cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) 
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)

cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)



ifdef CONFIG_CPU_SB1

ifdef CONFIG_SB1_PASS_1_WORKAROUNDS

KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds

KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds

endif

endif



# For smartmips configurations, there are hundreds of warnings due to ISA overrides

# in assembly and header files. smartmips is only supported for MIPS32r1 onwards

# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or

arch/mips/include/asm/fpu.h

+1 −1
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ static inline int __enable_fpu(enum fpu_mode mode) 
		goto fr_common;



	case FPU_64BIT:

#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) \

#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \

      || defined(CONFIG_64BIT))

		/* we only have a 32-bit FPU */

		return SIGFPE;

arch/mips/include/asm/mach-sibyte/war.h

+1 −2
Original line number Diff line number Diff line
@@ -13,8 +13,7 @@ 
#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0



#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \

    defined(CONFIG_SB1_PASS_2_WORKAROUNDS)

#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)



#ifndef __ASSEMBLY__

extern int sb1250_m3_workaround_needed(void);

arch/mips/include/uapi/asm/sigcontext.h

+2 −2
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 


/*

 * Keep this struct definition in sync with the sigcontext fragment

 * in arch/mips/tools/offset.c

 * in arch/mips/kernel/asm-offsets.c

 */

struct sigcontext {

	unsigned int		sc_regmask;	/* Unused */
@@ -46,7 +46,7 @@ struct sigcontext { 
#include <linux/posix_types.h>

/*

 * Keep this struct definition in sync with the sigcontext fragment

 * in arch/mips/tools/offset.c

 * in arch/mips/kernel/asm-offsets.c

 *

 * Warning: this structure illdefined with sc_badvaddr being just an unsigned

 * int so it was changed to unsigned long in 2.6.0-test1.  This may break

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