Commit 8bf9a701 authored Aug 30, 2015 by Christoffer Dall

arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs



The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only.
We currently simulate this behavior by writing a hardcoded value to the
register for the SGIs and PPIs on every write of these bits to the
register (ignoring what the guest actually wrote), and by writing the
same value as the reset value to the register.

This is a bit counter-intuitive, as the register is RO for these bits,
and we can just implement it that way, allowing us to control the value
of the bits purely in the reset code.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>

parent 9103617d

virt/kvm/arm/vgic.c

+2 −3

Original line number	Diff line number	Diff line
		@@ -690,10 +690,9 @@ bool vgic_handle_cfg_reg(u32 reg, struct kvm_exit_mmio mmio,
		vgic_reg_access(mmio, &val, offset,
		ACCESS_READ_VALUE \| ACCESS_WRITE_VALUE);
		if (mmio->is_write) {
		if (offset < 8) {
		reg = ~0U; / Force PPIs/SGIs to 1 */
		/* Ignore writes to read-only SGI and PPI bits */
		if (offset < 8)
		return false;
		}

		val = vgic_cfg_compress(val);
		if (offset & 4) {

Admin message