Commit 8bdbf169 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'arm/late' into arm/dt 

Include originally "late" updates for OMAP and Qualcomm,
now that it's not late any more.

* arm/late: (122 commits)
  ARM: OMAP2+: Drop legacy platform data for ti81xx edma
  ARM: dts: Configure interconnect target module for ti816x edma
  ARM: dts: Configure interconnect target module for dm814x tptc3
  ARM: dts: Configure interconnect target module for dm814x tptc2
  ARM: dts: Configure interconnect target module for dm814x tptc1
  ARM: dts: Configure interconnect target module for dm814x tptc0
  ARM: dts: Configure interconnect target module for dm814x tpcc
  ARM: OMAP2+: Drop legacy platform data for dm814x cpsw
  ARM: dts: Configure interconnect target module for dm814x cpsw
  clk: ti: Fix dm814x clkctrl for ethernet
  arm64: dts: qcom: sdm845-mtp: Relocate remoteproc firmware
  arm64: dts: sdm845: add IPA information
  arm64: dts: qcom: db845c: add analog audio support
  arm64: dts: qcom: sdm845: add pinctrl nodes for quat i2s
  arm64: dts: qcom: c630: Enable audio support
  arm64: dts: qcom: sdm845: add apr nodes
  arm64: dts: qcom: sdm845: add slimbus nodes
  arm64: dts: qcom: sc7180: Update reg names for SDHC
  arm64: dts: qcom: qcs404: Enable CQE support for eMMC
  arm64: dts: msm8916: Add fastrpc node
  ...
parents fdd41fac 56effbdd

Documentation/devicetree/bindings/arm/qcom.yaml

+8 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ description: | 
        apq8074

        apq8084

        apq8096

        ipq6018

        ipq8074

        mdm9615

        msm8916
@@ -41,6 +42,7 @@ description: | 
  The 'board' element must be one of the following strings:



        cdp

        cp01-c1

        dragonboard

        hk01

        idp
@@ -150,4 +152,10 @@ properties: 
          - enum:

              - qcom,sc7180-idp

          - const: qcom,sc7180



      - items:

          - enum:

              - qcom,ipq6018-cp01-c1

          - const: qcom,ipq6018



...

Documentation/devicetree/bindings/bus/ti-sysc.txt

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ Required standard properties: 
		"ti,sysc-dra7-mcasp"

		"ti,sysc-usb-host-fs"

		"ti,sysc-dra7-mcan"

		"ti,sysc-pruss"



- reg		shall have register areas implemented for the interconnect

		target module in question such as revision, sysc and syss

arch/arm/boot/dts/am33xx-l4.dtsi

+18 −3
Original line number Diff line number Diff line
@@ -759,12 +759,27 @@ 
			ranges = <0x0 0x200000 0x80000>;

		};



		target-module@300000 {			/* 0x4a300000, ap 9 04.0 */

			compatible = "ti,sysc";

			status = "disabled";

		pruss_tm: target-module@300000 {	/* 0x4a300000, ap 9 04.0 */

			compatible = "ti,sysc-pruss", "ti,sysc";

			reg = <0x326000 0x4>,

			      <0x326004 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |

					 SYSC_PRUSS_SUB_MWAIT)>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;

			clock-names = "fck";

			resets = <&prm_per 1>;

			reset-names = "rstctrl";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x300000 0x80000>;

			status = "disabled";

		};

	};

};

arch/arm/boot/dts/am33xx.dtsi

+88 −33
Original line number Diff line number Diff line
@@ -205,10 +205,19 @@ 
			reg = <0x48200000 0x1000>;

		};



		edma: edma@49000000 {

		target-module@49000000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49000000 0x4>;

			reg-names = "rev";

			clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49000000 0x10000>;



			edma: dma@0 {

				compatible = "ti,edma3-tpcc";

			ti,hwmods = "tpcc";

			reg =	<0x49000000 0x10000>;

				reg = <0 0x10000>;

				reg-names = "edma3_cc";

				interrupts = <12 13 14>;

				interrupt-names = "edma3_ccint", "edma3_mperr",
@@ -221,30 +230,76 @@ 


				ti,edma-memcpy-channels = <20 21>;

			};

		};



		edma_tptc0: tptc@49800000 {

		target-module@49800000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49800000 0x4>,

			      <0x49800010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49800000 0x100000>;



			edma_tptc0: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc0";

			reg =	<0x49800000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <112>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		edma_tptc1: tptc@49900000 {

		target-module@49900000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49900000 0x4>,

			      <0x49900010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49900000 0x100000>;



			edma_tptc1: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc1";

			reg =	<0x49900000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <113>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@49a00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49a00000 0x4>,

			      <0x49a00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49a00000 0x100000>;



		edma_tptc2: tptc@49a00000 {

			edma_tptc2: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc2";

			reg =	<0x49a00000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <114>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@47810000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

arch/arm/boot/dts/am4372.dtsi

+112 −67
Original line number Diff line number Diff line
@@ -197,10 +197,19 @@ 
				&pm_sram_data>;

		};



		edma: edma@49000000 {

		target-module@49000000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49000000 0x4>;

			reg-names = "rev";

			clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49000000 0x10000>;



			edma: dma@0 {

				compatible = "ti,edma3-tpcc";

			ti,hwmods = "tpcc";

			reg =	<0x49000000 0x10000>;

				reg = <0 0x10000>;

				reg-names = "edma3_cc";

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -215,30 +224,76 @@ 


				ti,edma-memcpy-channels = <58 59>;

			};

		};



		target-module@49800000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49800000 0x4>,

			      <0x49800010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49800000 0x100000>;



		edma_tptc0: tptc@49800000 {

			edma_tptc0: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc0";

			reg =	<0x49800000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		edma_tptc1: tptc@49900000 {

		target-module@49900000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49900000 0x4>,

			      <0x49900010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49900000 0x100000>;



			edma_tptc1: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc1";

			reg =	<0x49900000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		edma_tptc2: tptc@49a00000 {

		target-module@49a00000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x49a00000 0x4>,

			      <0x49a00010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x49a00000 0x100000>;



			edma_tptc2: dma@0 {

				compatible = "ti,edma3-tptc";

			ti,hwmods = "tptc2";

			reg =	<0x49a00000 0x100000>;

				reg = <0 0x100000>;

				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "edma3_tcerrint";

			};

		};



		target-module@47810000 {

			compatible = "ti,sysc-omap2", "ti,sysc";
@@ -356,6 +411,28 @@ 
			};

		};



		pruss_tm: target-module@54400000 {

			compatible = "ti,sysc-pruss", "ti,sysc";

			reg = <0x54426000 0x4>,

			      <0x54426004 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |

					 SYSC_PRUSS_SUB_MWAIT)>;

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;

			clock-names = "fck";

			resets = <&prm_per 1>;

			reset-names = "rstctrl";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x54400000 0x80000>;

		};



		gpmc: gpmc@50000000 {

			compatible = "ti,am3352-gpmc";

			ti,hwmods = "gpmc";
@@ -406,38 +483,6 @@ 
			};

		};



		dss: dss@4832a000 {

			compatible = "ti,omap3-dss";

			reg = <0x4832a000 0x200>;

			status = "disabled";

			ti,hwmods = "dss_core";

			clocks = <&disp_clk>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			dispc: dispc@4832a400 {

				compatible = "ti,omap3-dispc";

				reg = <0x4832a400 0x400>;

				interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

				ti,hwmods = "dss_dispc";

				clocks = <&disp_clk>;

				clock-names = "fck";



				max-memory-bandwidth = <230000000>;

			};



			rfbi: rfbi@4832a800 {

				compatible = "ti,omap3-rfbi";

				reg = <0x4832a800 0x100>;

				ti,hwmods = "dss_rfbi";

				clocks = <&disp_clk>;

				clock-names = "fck";

				status = "disabled";

			};

		};



		ocmcram: sram@40300000 {

			compatible = "mmio-sram";

			reg = <0x40300000 0x40000>; /* 256k */

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