Commit 8bc49f44 authored by 周琰杰 (Zhou Yanjie)'s avatar 周琰杰 (Zhou Yanjie) Committed by Linus Walleij
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dt-bindings: pinctrl: Add bindings for Ingenic X1830. 



Add the pinctrl bindings for the X1830 Soc from Ingenic.

Signed-off-by: default avatar周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1576426864-35348-6-git-send-email-zhouyanjie@wanyeetech.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent f742e5eb

Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt

+5 −3
Original line number Diff line number Diff line
@@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the 
naming scheme "PxN" where x is a character identifying the GPIO port with

which the pin is associated and N is an integer from 0 to 31 identifying the

pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and

PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO

ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780

contains 6 GPIO ports, PA to PF, for a total of 192 pins.

PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830

contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the

jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.





Required properties:
@@ -28,6 +28,7 @@ Required properties: 
    - "ingenic,x1000-pinctrl"

    - "ingenic,x1000e-pinctrl"

    - "ingenic,x1500-pinctrl"

    - "ingenic,x1830-pinctrl"

 - reg: Address range of the pinctrl registers.
@@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips): 
    - "ingenic,jz4770-gpio"

    - "ingenic,jz4780-gpio"

    - "ingenic,x1000-gpio"

    - "ingenic,x1830-gpio"

 - reg: The GPIO bank number.

 - interrupt-controller: Marks the device node as an interrupt controller.

 - interrupts: Interrupt specifier for the controllers interrupt.

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