Commit 8bb61306 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Move vlv/chv display irq code to a more logical place 



Reshuffle the code a bit to move the vlv/chv display irq functions away
from the main irq hooks, next to the other sub (de,gt,etc.) hooks.

v2: Rebased due to changes in vlv_display_irq_reset()

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1460476604-2035-1-git-send-email-ville.syrjala@linux.intel.com
parent 9918271e

drivers/gpu/drm/i915/i915_irq.c

+51 −51
Original line number Diff line number Diff line
@@ -3285,23 +3285,6 @@ static void gen5_gt_irq_reset(struct drm_device *dev) 
		GEN5_IRQ_RESET(GEN6_PM);

}



/* drm_dma.h hooks

*/

static void ironlake_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(HWSTAM, 0xffffffff);



	GEN5_IRQ_RESET(DE);

	if (IS_GEN7(dev))

		I915_WRITE(GEN7_ERR_INT, 0xffffffff);



	gen5_gt_irq_reset(dev);



	ibx_irq_reset(dev);

}



static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)

{

	enum pipe pipe;
@@ -3320,6 +3303,57 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 
	dev_priv->irq_mask = ~0;

}



static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)

{

	u32 pipestat_mask;

	u32 iir_mask;

	enum pipe pipe;



	pipestat_mask = PIPESTAT_INT_STATUS_MASK |

			PIPE_FIFO_UNDERRUN_STATUS;



	for_each_pipe(dev_priv, pipe)

		I915_WRITE(PIPESTAT(pipe), pipestat_mask);

	POSTING_READ(PIPESTAT(PIPE_A));



	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |

			PIPE_CRC_DONE_INTERRUPT_STATUS;



	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

	for_each_pipe(dev_priv, pipe)

		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);



	iir_mask = I915_DISPLAY_PORT_INTERRUPT |

		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |

		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;

	if (IS_CHERRYVIEW(dev_priv))

		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;

	dev_priv->irq_mask &= ~iir_mask;



	I915_WRITE(VLV_IIR, iir_mask);

	I915_WRITE(VLV_IIR, iir_mask);

	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);

	I915_WRITE(VLV_IMR, dev_priv->irq_mask);

	POSTING_READ(VLV_IMR);

}



/* drm_dma.h hooks

*/

static void ironlake_irq_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(HWSTAM, 0xffffffff);



	GEN5_IRQ_RESET(DE);

	if (IS_GEN7(dev))

		I915_WRITE(GEN7_ERR_INT, 0xffffffff);



	gen5_gt_irq_reset(dev);



	ibx_irq_reset(dev);

}



static void valleyview_irq_preinstall(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3656,40 +3690,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev) 
	return 0;

}



static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)

{

	u32 pipestat_mask;

	u32 iir_mask;

	enum pipe pipe;



	pipestat_mask = PIPESTAT_INT_STATUS_MASK |

			PIPE_FIFO_UNDERRUN_STATUS;



	for_each_pipe(dev_priv, pipe)

		I915_WRITE(PIPESTAT(pipe), pipestat_mask);

	POSTING_READ(PIPESTAT(PIPE_A));



	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |

			PIPE_CRC_DONE_INTERRUPT_STATUS;



	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

	for_each_pipe(dev_priv, pipe)

		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);



	iir_mask = I915_DISPLAY_PORT_INTERRUPT |

		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |

		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;

	if (IS_CHERRYVIEW(dev_priv))

		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;

	dev_priv->irq_mask &= ~iir_mask;



	I915_WRITE(VLV_IIR, iir_mask);

	I915_WRITE(VLV_IIR, iir_mask);

	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);

	I915_WRITE(VLV_IMR, dev_priv->irq_mask);

	POSTING_READ(VLV_IMR);

}



void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)

{

	assert_spin_locked(&dev_priv->irq_lock);

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