Commit 8b97bcb7 authored by Alex Elder's avatar Alex Elder Committed by David S. Miller
Browse files

net: ipa: clarify endpoint register macro constraints 



A handful of registers are valid only for RX endpoints, and some
others are valid only for TX endpoints.  For these endpoints, add
a comment above their defined offset macro that indicates the
endpoints to which they apply.

Extend the endpoint parameter naming convention as well, to make
these constraints more explicit.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 00b9102a

drivers/net/ipa/ipa_reg.h

+25 −18
Original line number Diff line number Diff line
@@ -32,10 +32,12 @@ struct ipa; 
 * parameter is supplied to the offset macro.  The "ee" value is a member of

 * the gsi_ee enumerated type.

 *

 * The offset of a register dependent on endpoint id is computed by a macro

 * that is supplied a parameter "ep".  The "ep" value is assumed to be less

 * than the maximum endpoint value for the current hardware, and that will

 * not exceed IPA_ENDPOINT_MAX.

 * The offset of a register dependent on endpoint ID is computed by a macro

 * that is supplied a parameter "ep", "txep", or "rxep".  A register with an

 * "ep" parameter is valid for any endpoint; a register with a "txep" or

 * "rxep" parameter is valid only for TX or RX endpoints, respectively.  The

 * "*ep" value is assumed to be less than the maximum valid endpoint ID

 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX.

 *

 * The offset of registers related to filter and route tables is computed

 * by a macro that is supplied a parameter "er".  The "er" represents an
@@ -292,11 +294,13 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 
#define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK	GENMASK(9, 4)

#define HDR_PAD_TO_ALIGNMENT_FMASK		GENMASK(13, 10)



#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(ep) \

					(0x00000818 + 0x0070 * (ep))

/* Valid only for RX (IPA producer) endpoints */

#define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \

					(0x00000818 + 0x0070 * (rxep))



#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(ep) \

					(0x00000820 + 0x0070 * (ep))

/* Valid only for TX (IPA consumer) endpoints */

#define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \

					(0x00000820 + 0x0070 * (txep))

#define MODE_FMASK				GENMASK(2, 0)

#define DEST_PIPE_INDEX_FMASK			GENMASK(8, 4)

#define BYTE_THRESHOLD_FMASK			GENMASK(27, 12)
@@ -315,19 +319,21 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 
#define AGGR_FORCE_CLOSE_FMASK			GENMASK(22, 22)

#define AGGR_HARD_BYTE_LIMIT_ENABLE_FMASK	GENMASK(24, 24)



#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(ep) \

					(0x0000082c +  0x0070 * (ep))

/* Valid only for RX (IPA producer) endpoints */

#define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \

					(0x0000082c +  0x0070 * (rxep))

#define HOL_BLOCK_EN_FMASK			GENMASK(0, 0)



/* The next register is valid only for RX (IPA producer) endpoints */

#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(ep) \

					(0x00000830 +  0x0070 * (ep))

/* Valid only for RX (IPA producer) endpoints */

#define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \

					(0x00000830 +  0x0070 * (rxep))

/* The next fields are present for IPA v4.2 only */

#define BASE_VALUE_FMASK			GENMASK(4, 0)

#define SCALE_FMASK				GENMASK(12, 8)



#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(ep) \

					(0x00000834 + 0x0070 * (ep))

/* Valid only for TX (IPA consumer) endpoints */

#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \

					(0x00000834 + 0x0070 * (txep))

#define DEAGGR_HDR_LEN_FMASK			GENMASK(5, 0)

#define PACKET_OFFSET_VALID_FMASK		GENMASK(7, 7)

#define PACKET_OFFSET_LOCATION_FMASK		GENMASK(13, 8)
@@ -337,8 +343,9 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 
					(0x00000838 + 0x0070 * (ep))

#define RSRC_GRP_FMASK				GENMASK(1, 0)



#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(ep) \

					(0x0000083c + 0x0070 * (ep))

/* Valid only for TX (IPA consumer) endpoints */

#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \

					(0x0000083c + 0x0070 * (txep))

#define HPS_SEQ_TYPE_FMASK			GENMASK(3, 0)

#define DPS_SEQ_TYPE_FMASK			GENMASK(7, 4)

#define HPS_REP_SEQ_TYPE_FMASK			GENMASK(11, 8)
@@ -352,7 +359,7 @@ static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 
/* The next field is present for IPA v4.0 and above */

#define STATUS_PKT_SUPPRESS_FMASK		GENMASK(9, 9)



/* "er" is either an endpoint id (for filters) or a route id (for routes) */

/* "er" is either an endpoint ID (for filters) or a route ID (for routes) */

#define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \

					(0x0000085c + 0x0070 * (er))

#define FILTER_HASH_MSK_SRC_ID_FMASK		GENMASK(0, 0)

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