Commit 8b955b0d authored by Eric W. Biederman's avatar Eric W. Biederman Committed by Linus Torvalds
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[PATCH] Initial generic hypertransport interrupt support 



This patch implements two functions ht_create_irq and ht_destroy_irq for
use by drivers.  Several other functions are implemented as helpers for
arch specific irq_chip handlers.

The driver for the card I tested this on isn't yet ready to be merged.
However this code is and hypertransport irqs are in use in a few other
places in the kernel.  Not that any of this will get merged before 2.6.19

Because the ipath-ht400 is slightly out of spec this code will need to be
generalized to work there.

I think all of the powerpc uses are for a plain interrupt controller in a
chipset so support for native hypertransport devices is a little less
interesting.

However I think this is a half way decent model on how to separate arch
specific and generic helper code, and I think this is a functional model of
how to get the architecture dependencies out of the msi code.

[akpm@osdl.org: Kconfig fix]
Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
Cc: Greg KH <greg@kroah.com>
Cc: Andi Kleen <ak@muc.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent e78d0169

arch/i386/kernel/io_apic.c

+90 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ 
#include <asm/i8259.h>

#include <asm/nmi.h>

#include <asm/msidef.h>

#include <asm/hypertransport.h>



#include <mach_apic.h>

#include <mach_apicdef.h>
@@ -2518,6 +2519,95 @@ struct msi_ops arch_msi_ops = { 


#endif /* CONFIG_PCI_MSI */



/*

 * Hypertransport interrupt support

 */

#ifdef CONFIG_HT_IRQ



#ifdef CONFIG_SMP



static void target_ht_irq(unsigned int irq, unsigned int dest)

{

	u32 low, high;

	low  = read_ht_irq_low(irq);

	high = read_ht_irq_high(irq);



	low  &= ~(HT_IRQ_LOW_DEST_ID_MASK);

	high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);



	low  |= HT_IRQ_LOW_DEST_ID(dest);

	high |= HT_IRQ_HIGH_DEST_ID(dest);



	write_ht_irq_low(irq, low);

	write_ht_irq_high(irq, high);

}



static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)

{

	unsigned int dest;

	cpumask_t tmp;



	cpus_and(tmp, mask, cpu_online_map);

	if (cpus_empty(tmp))

		tmp = TARGET_CPUS;



	cpus_and(mask, tmp, CPU_MASK_ALL);



	dest = cpu_mask_to_apicid(mask);



	target_ht_irq(irq, dest);

	set_native_irq_info(irq, mask);

}

#endif



static struct hw_interrupt_type ht_irq_chip = {

	.name		= "PCI-HT",

	.mask		= mask_ht_irq,

	.unmask		= unmask_ht_irq,

	.ack		= ack_ioapic_irq,

#ifdef CONFIG_SMP

	.set_affinity	= set_ht_irq_affinity,

#endif

	.retrigger	= ioapic_retrigger_irq,

};



int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)

{

	int vector;



	vector = assign_irq_vector(irq);

	if (vector >= 0) {

		u32 low, high;

		unsigned dest;

		cpumask_t tmp;



		cpus_clear(tmp);

		cpu_set(vector >> 8, tmp);

		dest = cpu_mask_to_apicid(tmp);



		high = 	HT_IRQ_HIGH_DEST_ID(dest);



		low =	HT_IRQ_LOW_BASE |

			HT_IRQ_LOW_DEST_ID(dest) |

			HT_IRQ_LOW_VECTOR(vector) |

			((INT_DEST_MODE == 0) ?

				HT_IRQ_LOW_DM_PHYSICAL :

				HT_IRQ_LOW_DM_LOGICAL) |

			HT_IRQ_LOW_RQEOI_EDGE |

			((INT_DELIVERY_MODE != dest_LowestPrio) ?

				HT_IRQ_LOW_MT_FIXED :

				HT_IRQ_LOW_MT_ARBITRATED) |

			HT_IRQ_LOW_IRQ_MASKED;



		write_ht_irq_low(irq, low);

		write_ht_irq_high(irq, high);



		set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq);

	}

	return vector;

}

#endif /* CONFIG_HT_IRQ */



/* --------------------------------------------------------------------------

                          ACPI-based IOAPIC Configuration

   -------------------------------------------------------------------------- */

arch/x86_64/kernel/io_apic.c

+96 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#include <asm/dma.h>

#include <asm/nmi.h>

#include <asm/msidef.h>

#include <asm/hypertransport.h>



static int assign_irq_vector(int irq, cpumask_t mask);
@@ -1772,6 +1773,101 @@ struct msi_ops arch_msi_ops = { 


#endif



/*

 * Hypertransport interrupt support

 */

#ifdef CONFIG_HT_IRQ



#ifdef CONFIG_SMP



static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)

{

	u32 low, high;

	low  = read_ht_irq_low(irq);

	high = read_ht_irq_high(irq);



	low  &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);

	high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);



	low  |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);

	high |= HT_IRQ_HIGH_DEST_ID(dest);



	write_ht_irq_low(irq, low);

	write_ht_irq_high(irq, high);

}



static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)

{

	unsigned int dest;

	cpumask_t tmp;

	int vector;



	cpus_and(tmp, mask, cpu_online_map);

	if (cpus_empty(tmp))

		tmp = TARGET_CPUS;



	cpus_and(mask, tmp, CPU_MASK_ALL);



	vector = assign_irq_vector(irq, mask);

	if (vector < 0)

		return;



	cpus_clear(tmp);

	cpu_set(vector >> 8, tmp);

	dest = cpu_mask_to_apicid(tmp);



	target_ht_irq(irq, dest, vector & 0xff);

	set_native_irq_info(irq, mask);

}

#endif



static struct hw_interrupt_type ht_irq_chip = {

	.name		= "PCI-HT",

	.mask		= mask_ht_irq,

	.unmask		= unmask_ht_irq,

	.ack		= ack_apic_edge,

#ifdef CONFIG_SMP

	.set_affinity	= set_ht_irq_affinity,

#endif

	.retrigger	= ioapic_retrigger_irq,

};



int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)

{

	int vector;



	vector = assign_irq_vector(irq, TARGET_CPUS);

	if (vector >= 0) {

		u32 low, high;

		unsigned dest;

		cpumask_t tmp;



		cpus_clear(tmp);

		cpu_set(vector >> 8, tmp);

		dest = cpu_mask_to_apicid(tmp);



		high = 	HT_IRQ_HIGH_DEST_ID(dest);



		low =	HT_IRQ_LOW_BASE |

			HT_IRQ_LOW_DEST_ID(dest) |

			HT_IRQ_LOW_VECTOR(vector) |

			((INT_DEST_MODE == 0) ?

				HT_IRQ_LOW_DM_PHYSICAL :

				HT_IRQ_LOW_DM_LOGICAL) |

			HT_IRQ_LOW_RQEOI_EDGE |

			((INT_DELIVERY_MODE != dest_LowestPrio) ?

				HT_IRQ_LOW_MT_FIXED :

				HT_IRQ_LOW_MT_ARBITRATED);



		write_ht_irq_low(irq, low);

		write_ht_irq_high(irq, high);



		set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq);

	}

	return vector;

}

#endif /* CONFIG_HT_IRQ */



/* --------------------------------------------------------------------------

                          ACPI-based IOAPIC Configuration

   -------------------------------------------------------------------------- */

drivers/pci/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -52,3 +52,12 @@ config PCI_DEBUG 


	  When in doubt, say N.



config HT_IRQ

	bool "Interrupts on hypertransport devices"

	default y

	depends on PCI_MSI

	depends on X86_LOCAL_APIC && X86_IO_APIC

	help

	   This allows native hypertransport devices to use interrupts.



	   If unsure say Y.

drivers/pci/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ obj-$(CONFIG_PPC32) += setup-irq.o 
obj-$(CONFIG_PPC64) += setup-bus.o

obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o

obj-$(CONFIG_X86_VISWS) += setup-irq.o

obj-$(CONFIG_HT_IRQ) += htirq.o



msiobj-y := msi.o

msiobj-$(CONFIG_IA64) += msi-apic.o

drivers/pci/htirq.c

0 → 100644
+189 −0
Original line number Diff line number Diff line 
/*

 * File:	htirq.c

 * Purpose:	Hypertransport Interrupt Capability

 *

 * Copyright (C) 2006 Linux Networx

 * Copyright (C) Eric Biederman <ebiederman@lnxi.com>

 */



#include <linux/irq.h>

#include <linux/pci.h>

#include <linux/spinlock.h>

#include <linux/slab.h>

#include <linux/gfp.h>



/* Global ht irq lock.

 *

 * This is needed to serialize access to the data port in hypertransport

 * irq capability.

 *

 * With multiple simultaneous hypertransport irq devices it might pay

 * to make this more fine grained.  But start with simple, stupid, and correct.

 */

static DEFINE_SPINLOCK(ht_irq_lock);



struct ht_irq_cfg {

	struct pci_dev *dev;

	unsigned pos;

	unsigned idx;

};



void write_ht_irq_low(unsigned int irq, u32 data)

{

	struct ht_irq_cfg *cfg = get_irq_data(irq);

	unsigned long flags;

	spin_lock_irqsave(&ht_irq_lock, flags);

	pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx);

	pci_write_config_dword(cfg->dev, cfg->pos + 4, data);

	spin_unlock_irqrestore(&ht_irq_lock, flags);

}



void write_ht_irq_high(unsigned int irq, u32 data)

{

	struct ht_irq_cfg *cfg = get_irq_data(irq);

	unsigned long flags;

	spin_lock_irqsave(&ht_irq_lock, flags);

	pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx + 1);

	pci_write_config_dword(cfg->dev, cfg->pos + 4, data);

	spin_unlock_irqrestore(&ht_irq_lock, flags);

}



u32 read_ht_irq_low(unsigned int irq)

{

	struct ht_irq_cfg *cfg = get_irq_data(irq);

	unsigned long flags;

	u32 data;

	spin_lock_irqsave(&ht_irq_lock, flags);

	pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx);

	pci_read_config_dword(cfg->dev, cfg->pos + 4, &data);

	spin_unlock_irqrestore(&ht_irq_lock, flags);

	return data;

}



u32 read_ht_irq_high(unsigned int irq)

{

	struct ht_irq_cfg *cfg = get_irq_data(irq);

	unsigned long flags;

	u32 data;

	spin_lock_irqsave(&ht_irq_lock, flags);

	pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx + 1);

	pci_read_config_dword(cfg->dev, cfg->pos + 4, &data);

	spin_unlock_irqrestore(&ht_irq_lock, flags);

	return data;

}



void mask_ht_irq(unsigned int irq)

{

	struct ht_irq_cfg *cfg;

	unsigned long flags;

	u32 data;



	cfg = get_irq_data(irq);



	spin_lock_irqsave(&ht_irq_lock, flags);

	pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx);

	pci_read_config_dword(cfg->dev, cfg->pos + 4, &data);

	data |= 1;

	pci_write_config_dword(cfg->dev, cfg->pos + 4, data);

	spin_unlock_irqrestore(&ht_irq_lock, flags);

}



void unmask_ht_irq(unsigned int irq)

{

	struct ht_irq_cfg *cfg;

	unsigned long flags;

	u32 data;



	cfg = get_irq_data(irq);



	spin_lock_irqsave(&ht_irq_lock, flags);

	pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx);

	pci_read_config_dword(cfg->dev, cfg->pos + 4, &data);

	data &= ~1;

	pci_write_config_dword(cfg->dev, cfg->pos + 4, data);

	spin_unlock_irqrestore(&ht_irq_lock, flags);

}



/**

 * ht_create_irq - create an irq and attach it to a device.

 * @dev: The hypertransport device to find the irq capability on.

 * @idx: Which of the possible irqs to attach to.

 *

 * ht_create_irq is needs to be called for all hypertransport devices

 * that generate irqs.

 *

 * The irq number of the new irq or a negative error value is returned.

 */

int ht_create_irq(struct pci_dev *dev, int idx)

{

	struct ht_irq_cfg *cfg;

	unsigned long flags;

	u32 data;

	int max_irq;

	int pos;

	int irq;



	pos = pci_find_capability(dev, PCI_CAP_ID_HT);

	while (pos) {

		u8 subtype;

		pci_read_config_byte(dev, pos + 3, &subtype);

		if (subtype == HT_CAPTYPE_IRQ)

			break;

		pos = pci_find_next_capability(dev, pos, PCI_CAP_ID_HT);

	}

	if (!pos)

		return -EINVAL;



	/* Verify the idx I want to use is in range */

	spin_lock_irqsave(&ht_irq_lock, flags);

	pci_write_config_byte(dev, pos + 2, 1);

	pci_read_config_dword(dev, pos + 4, &data);

	spin_unlock_irqrestore(&ht_irq_lock, flags);



	max_irq = (data >> 16) & 0xff;

	if ( idx > max_irq)

		return -EINVAL;



	cfg = kmalloc(sizeof(*cfg), GFP_KERNEL);

	if (!cfg)

		return -ENOMEM;



	cfg->dev = dev;

	cfg->pos = pos;

	cfg->idx = 0x10 + (idx * 2);



	irq = create_irq();

	if (irq < 0) {

		kfree(cfg);

		return -EBUSY;

	}

	set_irq_data(irq, cfg);



	if (arch_setup_ht_irq(irq, dev) < 0) {

		ht_destroy_irq(irq);

		return -EBUSY;

	}



	return irq;

}



/**

 * ht_destroy_irq - destroy an irq created with ht_create_irq

 *

 * This reverses ht_create_irq removing the specified irq from

 * existence.  The irq should be free before this happens.

 */

void ht_destroy_irq(unsigned int irq)

{

	struct ht_irq_cfg *cfg;



	cfg = get_irq_data(irq);

	set_irq_chip(irq, NULL);

	set_irq_data(irq, NULL);

	destroy_irq(irq);



	kfree(cfg);

}



EXPORT_SYMBOL(ht_create_irq);

EXPORT_SYMBOL(ht_destroy_irq);

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