Commit 8b6591fd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_platform_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 platform updates from Borislav Petkov:

 - Cleanup different aspects of the UV code and start adding support for
   the new UV5 class of systems (Mike Travis)

 - Use a flexible array for a dynamically sized struct uv_rtc_timer_head
   (Gustavo A. R. Silva)

* tag 'x86_platform_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/platform/uv: Update Copyrights to conform to HPE standards
  x86/platform/uv: Update for UV5 NMI MMR changes
  x86/platform/uv: Update UV5 TSC checking
  x86/platform/uv: Update node present counting
  x86/platform/uv: Update UV5 MMR references in UV GRU
  x86/platform/uv: Adjust GAM MMR references affected by UV5 updates
  x86/platform/uv: Update MMIOH references based on new UV5 MMRs
  x86/platform/uv: Add and decode Arch Type in UVsystab
  x86/platform/uv: Add UV5 direct references
  x86/platform/uv: Update UV MMRs for UV5
  drivers/misc/sgi-xp: Adjust references in UV kernel modules
  x86/platform/uv: Remove SCIR MMR references for UV systems
  x86/platform/uv: Remove UV BAU TLB Shootdown Handler
  x86/uv/time: Use a flexible array in struct uv_rtc_timer_head
parents 92a0610b 7a6d94f0

arch/x86/include/asm/idtentry.h

+0 −4
Original line number Diff line number Diff line
@@ -591,10 +591,6 @@ DECLARE_IDTENTRY_SYSVEC(CALL_FUNCTION_VECTOR, sysvec_call_function); 
#endif



#ifdef CONFIG_X86_LOCAL_APIC

# ifdef CONFIG_X86_UV

DECLARE_IDTENTRY_SYSVEC(UV_BAU_MESSAGE,			sysvec_uv_bau_message);

# endif



# ifdef CONFIG_X86_MCE_THRESHOLD

DECLARE_IDTENTRY_SYSVEC(THRESHOLD_APIC_VECTOR,		sysvec_threshold);

# endif

arch/x86/include/asm/uv/bios.h

+14 −3
Original line number Diff line number Diff line
@@ -5,7 +5,8 @@ 
/*

 * UV BIOS layer definitions.

 *

 *  Copyright (c) 2008-2009 Silicon Graphics, Inc.  All Rights Reserved.

 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP

 * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.

 * Copyright (c) Russ Anderson <rja@sgi.com>

 */
@@ -71,6 +72,11 @@ struct uv_gam_range_entry { 
	u32	limit;		/* PA bits 56:26 (UV_GAM_RANGE_SHFT) */

};



#define	UV_AT_SIZE	8	/* 7 character arch type + NULL char */

struct uv_arch_type_entry {

	char	archtype[UV_AT_SIZE];

};



#define	UV_SYSTAB_SIG			"UVST"

#define	UV_SYSTAB_VERSION_1		1	/* UV2/3 BIOS version */

#define	UV_SYSTAB_VERSION_UV4		0x400	/* UV4 BIOS base version */
@@ -79,10 +85,14 @@ struct uv_gam_range_entry { 
#define	UV_SYSTAB_VERSION_UV4_3		0x403	/* - GAM Range PXM Value */

#define	UV_SYSTAB_VERSION_UV4_LATEST	UV_SYSTAB_VERSION_UV4_3



#define	UV_SYSTAB_VERSION_UV5		0x500	/* UV5 GAM base version */

#define	UV_SYSTAB_VERSION_UV5_LATEST	UV_SYSTAB_VERSION_UV5



#define	UV_SYSTAB_TYPE_UNUSED		0	/* End of table (offset == 0) */

#define	UV_SYSTAB_TYPE_GAM_PARAMS	1	/* GAM PARAM conversions */

#define	UV_SYSTAB_TYPE_GAM_RNG_TBL	2	/* GAM entry table */

#define	UV_SYSTAB_TYPE_MAX		3

#define	UV_SYSTAB_TYPE_ARCH_TYPE	3	/* UV arch type */

#define	UV_SYSTAB_TYPE_MAX		4



/*

 * The UV system table describes specific firmware
@@ -133,6 +143,7 @@ extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *); 
extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus);



extern int uv_bios_init(void);

extern unsigned long get_uv_systab_phys(bool msg);



extern unsigned long sn_rtc_cycles_per_second;

extern int uv_type;

arch/x86/include/asm/uv/uv.h

+1 −3
Original line number Diff line number Diff line
@@ -35,10 +35,8 @@ extern int is_uv_hubbed(int uvtype); 
extern void uv_cpu_init(void);

extern void uv_nmi_init(void);

extern void uv_system_init(void);

extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,

						 const struct flush_tlb_info *info);



#else	/* X86_UV */

#else	/* !X86_UV */



static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; }

static inline bool is_early_uv_system(void)	{ return 0; }

arch/x86/include/asm/uv/uv_bau.h

deleted100644 → 0
+0 −755

File deleted.

Preview size limit exceeded, changes collapsed.

arch/x86/include/asm/uv/uv_hub.h

+68 −97
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 *

 * SGI UV architectural definitions

 *

 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP

 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.

 */
@@ -129,17 +130,6 @@ 
 */

#define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_BLADES * 2)



/* System Controller Interface Reg info */

struct uv_scir_s {

	struct timer_list timer;

	unsigned long	offset;

	unsigned long	last;

	unsigned long	idle_on;

	unsigned long	idle_off;

	unsigned char	state;

	unsigned char	enabled;

};



/* GAM (globally addressed memory) range table */

struct uv_gam_range_s {

	u32	limit;		/* PA bits 56:26 (GAM_RANGE_SHFT) */
@@ -155,6 +145,8 @@ struct uv_gam_range_s { 
 * available in the L3 cache on the cpu socket for the node.

 */

struct uv_hub_info_s {

	unsigned int		hub_type;

	unsigned char		hub_revision;

	unsigned long		global_mmr_base;

	unsigned long		global_mmr_shift;

	unsigned long		gpa_mask;
@@ -167,9 +159,9 @@ struct uv_hub_info_s { 
	unsigned char		m_val;

	unsigned char		n_val;

	unsigned char		gr_table_len;

	unsigned char		hub_revision;

	unsigned char		apic_pnode_shift;

	unsigned char		gpa_shift;

	unsigned char		nasid_shift;

	unsigned char		m_shift;

	unsigned char		n_lshift;

	unsigned int		gnode_extra;
@@ -191,16 +183,13 @@ struct uv_hub_info_s { 
struct uv_cpu_info_s {

	void			*p_uv_hub_info;

	unsigned char		blade_cpu_id;

	struct uv_scir_s	scir;

	void			*reserved;

};

DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);



#define uv_cpu_info		this_cpu_ptr(&__uv_cpu_info)

#define uv_cpu_info_per(cpu)	(&per_cpu(__uv_cpu_info, cpu))



#define	uv_scir_info		(&uv_cpu_info->scir)

#define	uv_cpu_scir_info(cpu)	(&uv_cpu_info_per(cpu)->scir)



/* Node specific hub common info struct */

extern void **__uv_hub_info_list;

static inline struct uv_hub_info_s *uv_hub_info_list(int node)
@@ -219,6 +208,17 @@ static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 
	return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info;

}



static inline int uv_hub_type(void)

{

	return uv_hub_info->hub_type;

}



static inline __init void uv_hub_type_set(int uvmask)

{

	uv_hub_info->hub_type = uvmask;

}





/*

 * HUB revision ranges for each UV HUB architecture.

 * This is a software convention - NOT the hardware revision numbers in
@@ -228,39 +228,31 @@ static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 
#define UV3_HUB_REVISION_BASE		5

#define UV4_HUB_REVISION_BASE		7

#define UV4A_HUB_REVISION_BASE		8	/* UV4 (fixed) rev 2 */

#define UV5_HUB_REVISION_BASE		9



static inline int is_uv2_hub(void)

{

	return is_uv_hubbed(uv(2));

}



static inline int is_uv3_hub(void)

{

	return is_uv_hubbed(uv(3));

}

static inline int is_uv(int uvmask) { return uv_hub_type() & uvmask; }

static inline int is_uv1_hub(void) { return 0; }

static inline int is_uv2_hub(void) { return is_uv(UV2); }

static inline int is_uv3_hub(void) { return is_uv(UV3); }

static inline int is_uv4a_hub(void) { return is_uv(UV4A); }

static inline int is_uv4_hub(void) { return is_uv(UV4); }

static inline int is_uv5_hub(void) { return is_uv(UV5); }



/* First test "is UV4A", then "is UV4" */

static inline int is_uv4a_hub(void)

{

	if (is_uv_hubbed(uv(4)))

		return (uv_hub_info->hub_revision == UV4A_HUB_REVISION_BASE);

	return 0;

}

/*

 * UV4A is a revision of UV4.  So on UV4A, both is_uv4_hub() and

 * is_uv4a_hub() return true, While on UV4, only is_uv4_hub()

 * returns true.  So to get true results, first test if is UV4A,

 * then test if is UV4.

 */



static inline int is_uv4_hub(void)

{

	return is_uv_hubbed(uv(4));

}

/* UVX class: UV2,3,4 */

static inline int is_uvx_hub(void) { return is_uv(UVX); }



static inline int is_uvx_hub(void)

{

	return (is_uv_hubbed(-2) >= uv(2));

}

/* UVY class: UV5,..? */

static inline int is_uvy_hub(void) { return is_uv(UVY); }



static inline int is_uv_hub(void)

{

	return is_uvx_hub();

}

/* Any UV Hubbed System */

static inline int is_uv_hub(void) { return is_uv(UV_ANY); }



union uvh_apicid {

    unsigned long       v;
@@ -282,9 +274,11 @@ union uvh_apicid { 
 *		g -  GNODE (full 15-bit global nasid, right shifted 1)

 *		p -  PNODE (local part of nsids, right shifted 1)

 */

#define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)

#define UV_NASID_TO_PNODE(n)		\

		(((n) >> uv_hub_info->nasid_shift) & uv_hub_info->pnode_mask)

#define UV_PNODE_TO_GNODE(p)		((p) |uv_hub_info->gnode_extra)

#define UV_PNODE_TO_NASID(p)		(UV_PNODE_TO_GNODE(p) << 1)

#define UV_PNODE_TO_NASID(p)		\

		(UV_PNODE_TO_GNODE(p) << uv_hub_info->nasid_shift)



#define UV2_LOCAL_MMR_BASE		0xfa000000UL

#define UV2_GLOBAL_MMR32_BASE		0xfc000000UL
@@ -297,29 +291,42 @@ union uvh_apicid { 
#define UV3_GLOBAL_MMR32_SIZE		(32UL * 1024 * 1024)



#define UV4_LOCAL_MMR_BASE		0xfa000000UL

#define UV4_GLOBAL_MMR32_BASE		0xfc000000UL

#define UV4_GLOBAL_MMR32_BASE		0

#define UV4_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)

#define UV4_GLOBAL_MMR32_SIZE		(16UL * 1024 * 1024)

#define UV4_GLOBAL_MMR32_SIZE		0



#define UV5_LOCAL_MMR_BASE		0xfa000000UL

#define UV5_GLOBAL_MMR32_BASE		0

#define UV5_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)

#define UV5_GLOBAL_MMR32_SIZE		0



#define UV_LOCAL_MMR_BASE		(				\

					is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \

					is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \

					/*is_uv4_hub*/ UV4_LOCAL_MMR_BASE)

					is_uv(UV2) ? UV2_LOCAL_MMR_BASE : \

					is_uv(UV3) ? UV3_LOCAL_MMR_BASE : \

					is_uv(UV4) ? UV4_LOCAL_MMR_BASE : \

					is_uv(UV5) ? UV5_LOCAL_MMR_BASE : \

					0)



#define UV_GLOBAL_MMR32_BASE		(				\

					is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \

					is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \

					/*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE)

					is_uv(UV2) ? UV2_GLOBAL_MMR32_BASE : \

					is_uv(UV3) ? UV3_GLOBAL_MMR32_BASE : \

					is_uv(UV4) ? UV4_GLOBAL_MMR32_BASE : \

					is_uv(UV5) ? UV5_GLOBAL_MMR32_BASE : \

					0)



#define UV_LOCAL_MMR_SIZE		(				\

					is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \

					is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \

					/*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE)

					is_uv(UV2) ? UV2_LOCAL_MMR_SIZE : \

					is_uv(UV3) ? UV3_LOCAL_MMR_SIZE : \

					is_uv(UV4) ? UV4_LOCAL_MMR_SIZE : \

					is_uv(UV5) ? UV5_LOCAL_MMR_SIZE : \

					0)



#define UV_GLOBAL_MMR32_SIZE		(				\

					is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \

					is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \

					/*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE)

					is_uv(UV2) ? UV2_GLOBAL_MMR32_SIZE : \

					is_uv(UV3) ? UV3_GLOBAL_MMR32_SIZE : \

					is_uv(UV4) ? UV4_GLOBAL_MMR32_SIZE : \

					is_uv(UV5) ? UV5_GLOBAL_MMR32_SIZE : \

					0)



#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
@@ -720,7 +727,7 @@ extern void uv_nmi_setup_hubless(void); 
#define UVH_TSC_SYNC_SHIFT_UV2K	16	/* UV2/3k have different bits */

#define UVH_TSC_SYNC_MASK	3	/* 0011 */

#define UVH_TSC_SYNC_VALID	3	/* 0011 */

#define UVH_TSC_SYNC_INVALID	2	/* 0010 */

#define UVH_TSC_SYNC_UNKNOWN	0	/* 0000 */



/* BMC sets a bit this MMR non-zero before sending an NMI */

#define UVH_NMI_MMR		UVH_BIOS_KERNEL_MMR
@@ -728,19 +735,6 @@ extern void uv_nmi_setup_hubless(void); 
#define UVH_NMI_MMR_SHIFT	63

#define UVH_NMI_MMR_TYPE	"SCRATCH5"



/* Newer SMM NMI handler, not present in all systems */

#define UVH_NMI_MMRX		UVH_EVENT_OCCURRED0

#define UVH_NMI_MMRX_CLEAR	UVH_EVENT_OCCURRED0_ALIAS

#define UVH_NMI_MMRX_SHIFT	UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT

#define UVH_NMI_MMRX_TYPE	"EXTIO_INT0"



/* Non-zero indicates newer SMM NMI handler present */

#define UVH_NMI_MMRX_SUPPORTED	UVH_EXTIO_INT0_BROADCAST



/* Indicates to BIOS that we want to use the newer SMM NMI handler */

#define UVH_NMI_MMRX_REQ	UVH_BIOS_KERNEL_MMR_ALIAS_2

#define UVH_NMI_MMRX_REQ_SHIFT	62



struct uv_hub_nmi_s {

	raw_spinlock_t	nmi_lock;

	atomic_t	in_nmi;		/* flag this node in UV NMI IRQ */
@@ -772,29 +766,6 @@ DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 
#define	UV_NMI_STATE_DUMP		2

#define	UV_NMI_STATE_DUMP_DONE		3



/* Update SCIR state */

static inline void uv_set_scir_bits(unsigned char value)

{

	if (uv_scir_info->state != value) {

		uv_scir_info->state = value;

		uv_write_local_mmr8(uv_scir_info->offset, value);

	}

}



static inline unsigned long uv_scir_offset(int apicid)

{

	return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);

}



static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)

{

	if (uv_cpu_scir_info(cpu)->state != value) {

		uv_write_global_mmr8(uv_cpu_to_pnode(cpu),

				uv_cpu_scir_info(cpu)->offset, value);

		uv_cpu_scir_info(cpu)->state = value;

	}

}



/*

 * Get the minimum revision number of the hub chips within the partition.

 * (See UVx_HUB_REVISION_BASE above for specific values.)

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