Unverified Commit 8b2f57d6 authored by Mark Brown's avatar Mark Brown
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Merge series "ASoC: sun8i-codec driver cleanup" from Samuel Holland <samuel@sholland.org>: 

Now that the fixes series is merged, here is a series of small cleanups
to the sun8i-codec driver. These help shorten the patch stack for the
next series, which will add support for the other two DAIs in this
codec: AIF2 and AIF3.

Samuel Holland (9):
  ASoC: sun8i-codec: Remove extraneous widgets
  ASoC: sun8i-codec: Fix AIF1 MODCLK widget name
  ASoC: sun8i-codec: Fix AIF1_ADCDAT_CTRL field names
  ASoC: sun8i-codec: Fix AIF1_MXR_SRC field names
  ASoC: sun8i-codec: Fix ADC_DIG_CTRL field name
  ASoC: sun8i-codec: Fix field bit number indentation
  ASoC: sun8i-codec: Sort masks in a consistent order
  ASoC: sun8i-codec: Attach the bus clock to the regmap
  ASoC: sun8i-codec: Manage module clock via DAPM

 sound/soc/sunxi/sun8i-codec.c | 104 ++++++++++++----------------------
 1 file changed, 37 insertions(+), 67 deletions(-)

--
2.26.2
parents daa90764 6b3bb3c8

sound/soc/sunxi/sun8i-codec.c

+37 −67
Original line number Diff line number Diff line
@@ -49,22 +49,22 @@ 
#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16		(1 << 4)

#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT		2

#define SUN8I_AIF1_ADCDAT_CTRL				0x044

#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA		15

#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA		14

#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA		15

#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA		14

#define SUN8I_AIF1_DACDAT_CTRL				0x048

#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA		15

#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA		14

#define SUN8I_AIF1_MXR_SRC				0x04c

#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L	15

#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL	14

#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL		13

#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR	12

#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L	15

#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL	14

#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL		13

#define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR	12

#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R	11

#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR	10

#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR		9

#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL	8

#define SUN8I_ADC_DIG_CTRL				0x100

#define SUN8I_ADC_DIG_CTRL_ENDA			15

#define SUN8I_ADC_DIG_CTRL_ENAD				15

#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS			2

#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY			1

#define SUN8I_DAC_DIG_CTRL				0x120
@@ -81,10 +81,10 @@ 


#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK		GENMASK(15, 12)

#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK		GENMASK(11, 8)

#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK	GENMASK(3, 2)

#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK	GENMASK(5, 4)

#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK	GENMASK(8, 6)

#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK	GENMASK(12, 9)

#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK	GENMASK(8, 6)

#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK	GENMASK(5, 4)

#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK	GENMASK(3, 2)



struct sun8i_codec_quirks {

	bool legacy_widgets	: 1;
@@ -94,7 +94,6 @@ struct sun8i_codec_quirks { 
struct sun8i_codec {

	struct regmap			*regmap;

	struct clk			*clk_module;

	struct clk			*clk_bus;

	const struct sun8i_codec_quirks	*quirks;

};
@@ -103,35 +102,15 @@ static int sun8i_codec_runtime_resume(struct device *dev) 
	struct sun8i_codec *scodec = dev_get_drvdata(dev);

	int ret;



	ret = clk_prepare_enable(scodec->clk_module);

	if (ret) {

		dev_err(dev, "Failed to enable the module clock\n");

		return ret;

	}



	ret = clk_prepare_enable(scodec->clk_bus);

	if (ret) {

		dev_err(dev, "Failed to enable the bus clock\n");

		goto err_disable_modclk;

	}



	regcache_cache_only(scodec->regmap, false);



	ret = regcache_sync(scodec->regmap);

	if (ret) {

		dev_err(dev, "Failed to sync regmap cache\n");

		goto err_disable_clk;

		return ret;

	}



	return 0;



err_disable_clk:

	clk_disable_unprepare(scodec->clk_bus);



err_disable_modclk:

	clk_disable_unprepare(scodec->clk_module);



	return ret;

}



static int sun8i_codec_runtime_suspend(struct device *dev)
@@ -141,9 +120,6 @@ static int sun8i_codec_runtime_suspend(struct device *dev) 
	regcache_cache_only(scodec->regmap, true);

	regcache_mark_dirty(scodec->regmap);



	clk_disable_unprepare(scodec->clk_module);

	clk_disable_unprepare(scodec->clk_bus);



	return 0;

}
@@ -374,26 +350,28 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { 
static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = {

	SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",

			SUN8I_AIF1_MXR_SRC,

			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L,

			SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L,

			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),

	SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC,

			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL,

			SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL,

			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),

	SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",

			SUN8I_AIF1_MXR_SRC,

			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL,

			SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL,

			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),

	SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",

			SUN8I_AIF1_MXR_SRC,

			SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR,

			SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR,

			SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),

};



static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {

	SND_SOC_DAPM_CLOCK_SUPPLY("mod"),



	/* Digital parts of the DACs and ADC */

	SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,

			    0, NULL, 0),

	SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENDA,

	SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENAD,

			    0, NULL, 0),



	/* AIF "DAC" Inputs */
@@ -407,10 +385,10 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { 
	/* AIF "ADC" Outputs */

	SND_SOC_DAPM_AIF_IN("AIF1 AD0L", "Capture", 0,

			    SUN8I_AIF1_ADCDAT_CTRL,

			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0),

			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0),

	SND_SOC_DAPM_AIF_IN("AIF1 AD0R", "Capture", 0,

			    SUN8I_AIF1_ADCDAT_CTRL,

			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),

			    SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0),



	/* ADC Inputs (connected to analog codec DAPM context) */

	SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0),
@@ -431,7 +409,7 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { 
			sun8i_input_mixer_controls),



	/* Clocks */

	SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,

	SND_SOC_DAPM_SUPPLY("MODCLK AIF1", SUN8I_MOD_CLK_ENA,

			    SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),

	SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,

			    SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
@@ -455,24 +433,22 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { 
			    SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),

	SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL,

			    SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0),



	SND_SOC_DAPM_MIC("Headset Mic", NULL),

	SND_SOC_DAPM_MIC("Mic", NULL),



};



static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {

	/* Clock Routes */

	{ "AIF1", NULL, "mod" },



	{ "AIF1", NULL, "SYSCLK AIF1" },

	{ "AIF1 PLL", NULL, "AIF1" },

	{ "SYSCLK", NULL, "AIF1 PLL" },



	{ "RST AIF1", NULL, "SYSCLK" },

	{ "MODCLK AFI1", NULL, "RST AIF1" },

	{ "AIF1 AD0L", NULL, "MODCLK AFI1" },

	{ "AIF1 AD0R", NULL, "MODCLK AFI1" },

	{ "AIF1 DA0L", NULL, "MODCLK AFI1" },

	{ "AIF1 DA0R", NULL, "MODCLK AFI1" },

	{ "MODCLK AIF1", NULL, "RST AIF1" },

	{ "AIF1 AD0L", NULL, "MODCLK AIF1" },

	{ "AIF1 AD0R", NULL, "MODCLK AIF1" },

	{ "AIF1 DA0L", NULL, "MODCLK AIF1" },

	{ "AIF1 DA0R", NULL, "MODCLK AIF1" },



	{ "RST DAC", NULL, "SYSCLK" },

	{ "MODCLK DAC", NULL, "RST DAC" },
@@ -616,19 +592,13 @@ static int sun8i_codec_probe(struct platform_device *pdev) 
		return PTR_ERR(scodec->clk_module);

	}



	scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");

	if (IS_ERR(scodec->clk_bus)) {

		dev_err(&pdev->dev, "Failed to get the bus clock\n");

		return PTR_ERR(scodec->clk_bus);

	}



	base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(base)) {

		dev_err(&pdev->dev, "Failed to map the registers\n");

		return PTR_ERR(base);

	}



	scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,

	scodec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", base,

						   &sun8i_codec_regmap_config);

	if (IS_ERR(scodec->regmap)) {

		dev_err(&pdev->dev, "Failed to create our regmap\n");

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