Commit 8b1d9ec4 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Masahiro Yamada
Browse files

ARM: dts: uniphier: Add USB3 controller nodes for Pro5 



Add USB3 controller nodes for Pro5 SoC and the boards.

Pro5 SoC has 2 controllers. USB0 includes 1 SS-PHY and 1 HS-PHY, and USB1
includes 1 SS-PHY and 2 HS-PHY.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 0d473705

arch/arm/boot/dts/uniphier-pro5.dtsi

+148 −0
Original line number Diff line number Diff line
@@ -453,6 +453,154 @@ 
			};

		};



		usb0: usb@65a00000 {

			compatible = "socionext,uniphier-dwc3", "snps,dwc3";

			status = "disabled";

			reg = <0x65a00000 0xcd00>;

			interrupt-names = "host";

			interrupts = <0 134 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb0>;

			clock-names = "ref", "bus_early", "suspend";

			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;

			resets = <&usb0_rst 15>;

			phys = <&usb0_hsphy0>, <&usb0_ssphy0>;

			dr_mode = "host";

		};



		usb-glue@65b00000 {

			compatible = "socionext,uniphier-pro5-dwc3-glue",

				     "simple-mfd";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x65b00000 0x400>;



			usb0_rst: reset@0 {

				compatible = "socionext,uniphier-pro5-usb3-reset";

				reg = <0x0 0x4>;

				#reset-cells = <1>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 14>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 14>;

			};



			usb0_vbus0: regulator@100 {

				compatible = "socionext,uniphier-pro5-usb3-regulator";

				reg = <0x100 0x10>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 14>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 14>;

			};



			usb0_hsphy0: hs-phy@280 {

				compatible = "socionext,uniphier-pro5-usb3-hsphy";

				reg = <0x280 0x10>;

				#phy-cells = <0>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 14>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 14>;

				vbus-supply = <&usb0_vbus0>;

			};



			usb0_ssphy0: ss-phy@380 {

				compatible = "socionext,uniphier-pro5-usb3-ssphy";

				reg = <0x380 0x10>;

				#phy-cells = <0>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 14>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 14>;

				vbus-supply = <&usb0_vbus0>;

			};

		};



		usb1: usb@65c00000 {

			compatible = "socionext,uniphier-dwc3", "snps,dwc3";

			status = "disabled";

			reg = <0x65c00000 0xcd00>;

			interrupt-names = "host";

			interrupts = <0 137 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;

			clock-names = "ref", "bus_early", "suspend";

			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;

			resets = <&usb1_rst 15>;

			phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;

			dr_mode = "host";

		};



		usb-glue@65d00000 {

			compatible = "socionext,uniphier-pro5-dwc3-glue",

				     "simple-mfd";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x65d00000 0x400>;



			usb1_rst: reset@0 {

				compatible = "socionext,uniphier-pro5-usb3-reset";

				reg = <0x0 0x4>;

				#reset-cells = <1>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 15>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 15>;

			};



			usb1_vbus0: regulator@100 {

				compatible = "socionext,uniphier-pro5-usb3-regulator";

				reg = <0x100 0x10>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 15>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 15>;

			};



			usb1_vbus1: regulator@110 {

				compatible = "socionext,uniphier-pro5-usb3-regulator";

				reg = <0x110 0x10>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 15>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 15>;

			};



			usb1_hsphy0: hs-phy@280 {

				compatible = "socionext,uniphier-pro5-usb3-hsphy";

				reg = <0x280 0x10>;

				#phy-cells = <0>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 15>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 15>;

				vbus-supply = <&usb1_vbus0>;

			};



			usb1_hsphy1: hs-phy@290 {

				compatible = "socionext,uniphier-pro5-usb3-hsphy";

				reg = <0x290 0x10>;

				#phy-cells = <0>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 15>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 15>;

				vbus-supply = <&usb1_vbus1>;

			};



			usb1_ssphy0: ss-phy@380 {

				compatible = "socionext,uniphier-pro5-usb3-ssphy";

				reg = <0x380 0x10>;

				#phy-cells = <0>;

				clock-names = "gio", "link";

				clocks = <&sys_clk 12>, <&sys_clk 15>;

				reset-names = "gio", "link";

				resets = <&sys_rst 12>, <&sys_rst 15>;

				vbus-supply = <&usb1_vbus0>;

			};

		};



		nand: nand-controller@68000000 {

			compatible = "socionext,uniphier-denali-nand-v5b";

			status = "disabled";

CRA Git | Maintained and supported by SUSTech CRA and CCSE