Commit 8ab54ed6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irqchip fixes from Thomas Gleixner:
 "Another set of ARM SoC related irqchip fixes:
   - Plug a memory leak in gicv3-its
   - Limit features to the root gic interrupt controller
   - Add a missing barrier in the gic-v3 IAR access
   - Another compile test fix for sun4i"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
  irqchip/gic: Only set the EOImodeNS bit for the root controller
  irqchip/gic: Only populate set_affinity for the root controller
  irqchip/gicv3-its: Fix memory leak in its_free_tables()
  irqchip/sun4i: Fix compilation outside of arch/arm
parents 2d23e61f 49b245ef

arch/arm64/include/asm/arch_gicv3.h

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void) 
	u64 irqstat;



	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	dsb(sy);

	return irqstat;

}

drivers/irqchip/irq-gic-v3-its.c

+11 −6
Original line number Diff line number Diff line
@@ -66,7 +66,10 @@ struct its_node { 
	unsigned long		phys_base;

	struct its_cmd_block	*cmd_base;

	struct its_cmd_block	*cmd_write;

	void			*tables[GITS_BASER_NR_REGS];

	struct {

		void		*base;

		u32		order;

	} tables[GITS_BASER_NR_REGS];

	struct its_collection	*collections;

	struct list_head	its_device_list;

	u64			flags;
@@ -807,9 +810,10 @@ static void its_free_tables(struct its_node *its) 
	int i;



	for (i = 0; i < GITS_BASER_NR_REGS; i++) {

		if (its->tables[i]) {

			free_page((unsigned long)its->tables[i]);

			its->tables[i] = NULL;

		if (its->tables[i].base) {

			free_pages((unsigned long)its->tables[i].base,

				   its->tables[i].order);

			its->tables[i].base = NULL;

		}

	}

}
@@ -890,7 +894,8 @@ retry_alloc_baser: 
			goto out_free;

		}



		its->tables[i] = base;

		its->tables[i].base = base;

		its->tables[i].order = order;



retry_baser:

		val = (virt_to_phys(base) 				 |
@@ -940,7 +945,7 @@ retry_baser: 
			 * something is horribly wrong...

			 */

			free_pages((unsigned long)base, order);

			its->tables[i] = NULL;

			its->tables[i].base = NULL;



			switch (psz) {

			case SZ_16K:

drivers/irqchip/irq-gic.c

+6 −7
Original line number Diff line number Diff line
@@ -384,9 +384,6 @@ static struct irq_chip gic_chip = { 
	.irq_unmask		= gic_unmask_irq,

	.irq_eoi		= gic_eoi_irq,

	.irq_set_type		= gic_set_type,

#ifdef CONFIG_SMP

	.irq_set_affinity	= gic_set_affinity,

#endif

	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,

	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,

	.flags			= IRQCHIP_SET_TYPE_MASKED |
@@ -400,9 +397,6 @@ static struct irq_chip gic_eoimode1_chip = { 
	.irq_unmask		= gic_unmask_irq,

	.irq_eoi		= gic_eoimode1_eoi_irq,

	.irq_set_type		= gic_set_type,

#ifdef CONFIG_SMP

	.irq_set_affinity	= gic_set_affinity,

#endif

	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,

	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,

	.irq_set_vcpu_affinity	= gic_irq_set_vcpu_affinity,
@@ -443,7 +437,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic) 
	u32 bypass = 0;

	u32 mode = 0;



	if (static_key_true(&supports_deactivate))

	if (gic == &gic_data[0] && static_key_true(&supports_deactivate))

		mode = GIC_CPU_CTRL_EOImodeNS;



	/*
@@ -1039,6 +1033,11 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, 
		gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);

	}



#ifdef CONFIG_SMP

	if (gic_nr == 0)

		gic->chip.irq_set_affinity = gic_set_affinity;

#endif



#ifdef CONFIG_GIC_NON_BANKED

	if (percpu_offset) { /* Frankein-GIC without banked registers... */

		unsigned int cpu;

drivers/irqchip/irq-sun4i.c

+0 −1
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 
#include <linux/of_irq.h>



#include <asm/exception.h>

#include <asm/mach/irq.h>



#define SUN4I_IRQ_VECTOR_REG		0x00

#define SUN4I_IRQ_PROTECTION_REG	0x08

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