Commit 8aaca197 authored May 23, 2018 by Rabie Loulou Committed by Saeed Mahameed Dec 14, 2018

net/mlx5: Allow co-enablement of uplink LAG and SRIOV



Enable setting uplink LAG if sriov is enabled on both ports in switchdev
mode.

Once the sriov mode is changed from switchdev for any of the ports, the
LAG instance is disabled.

Signed-off-by: Rabie Loulou <rabiel@mellanox.com>
Signed-off-by: Aviv Heller <avivh@mellanox.com>
Signed-off-by: Jianbo Liu <jianbol@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

parent eff849b2

drivers/net/ethernet/mellanox/mlx5/core/eswitch.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -2232,8 +2232,10 @@ EXPORT_SYMBOL_GPL(mlx5_eswitch_mode);

		bool mlx5_esw_lag_prereq(struct mlx5_core_dev dev0, struct mlx5_core_dev dev1)
		{
		if (dev0->priv.eswitch->mode == SRIOV_NONE &&
		dev1->priv.eswitch->mode == SRIOV_NONE)
		if ((dev0->priv.eswitch->mode == SRIOV_NONE &&
		dev1->priv.eswitch->mode == SRIOV_NONE) \|\|
		(dev0->priv.eswitch->mode == SRIOV_OFFLOADS &&
		dev1->priv.eswitch->mode == SRIOV_OFFLOADS))
		return true;

		return false;

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