drm/amdgpu: use the AV1 defines for VCN 3.0 (8a410da6) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+8 −8

Original line number	Diff line number	Diff line
		@@ -746,18 +746,18 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
		\| UVD_SUVD_CGC_GATE__IME_HEVC_MASK
		\| UVD_SUVD_CGC_GATE__EFC_MASK
		\| UVD_SUVD_CGC_GATE__SAOE_MASK
		\| 0x08000000
		\| UVD_SUVD_CGC_GATE__SRE_AV1_MASK
		\| UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
		\| UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
		\| 0x40000000
		\| UVD_SUVD_CGC_GATE__SCM_AV1_MASK
		\| UVD_SUVD_CGC_GATE__SMPA_MASK);
		WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);

		data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
		data \|= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
		\| UVD_SUVD_CGC_GATE2__MPBE1_MASK
		\| 0x00000004
		\| 0x00000008
		\| UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
		\| UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
		\| UVD_SUVD_CGC_GATE2__MPC1_MASK);
		WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);

		@@ -776,8 +776,8 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
		\| UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
		\| 0x00008000
		\| 0x00010000
		\| UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
		\| UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
		@@ -892,8 +892,8 @@ static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
		\| UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
		\| 0x00008000
		\| 0x00010000
		\| UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
		\| UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
		\| UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);

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