Commit 8a398d75 authored by Jonas Gorski's avatar Jonas Gorski Committed by Ralf Baechle
Browse files

MIPS: BCM63XX: remove duplicate spi register definitions 



BCM6338 and BCM6348, and BCM6358 and everything after that share the
same register layout. To not have to redefine them for each new chip
and keep the code size small, only use the definitions for the first
chip with the certain layout.

Signed-off-by: default avatarJonas Gorski <jogo@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5006/


Acked-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 41ef2d56

arch/mips/bcm63xx/dev-spi.c

+6 −18
Original line number Diff line number Diff line
@@ -22,10 +22,6 @@ 
/*

 * register offsets

 */

static const unsigned long bcm6338_regs_spi[] = {

	__GEN_SPI_REGS_TABLE(6338)

};



static const unsigned long bcm6348_regs_spi[] = {

	__GEN_SPI_REGS_TABLE(6348)

};
@@ -34,23 +30,15 @@ static const unsigned long bcm6358_regs_spi[] = { 
	__GEN_SPI_REGS_TABLE(6358)

};



static const unsigned long bcm6368_regs_spi[] = {

	__GEN_SPI_REGS_TABLE(6368)

};



const unsigned long *bcm63xx_regs_spi;

EXPORT_SYMBOL(bcm63xx_regs_spi);



static __init void bcm63xx_spi_regs_init(void)

{

	if (BCMCPU_IS_6338())

		bcm63xx_regs_spi = bcm6338_regs_spi;

	if (BCMCPU_IS_6348())

	if (BCMCPU_IS_6338() || BCMCPU_IS_6348())

		bcm63xx_regs_spi = bcm6348_regs_spi;

	if (BCMCPU_IS_6358())

	if (BCMCPU_IS_6358() || BCMCPU_IS_6368())

		bcm63xx_regs_spi = bcm6358_regs_spi;

	if (BCMCPU_IS_6368())

		bcm63xx_regs_spi = bcm6368_regs_spi;

}

#else

static __init void bcm63xx_spi_regs_init(void) { }
@@ -104,10 +92,10 @@ int __init bcm63xx_spi_register(void) 
	spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);



	if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {

		spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;

		spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;

		spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;

		spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;

		spi_resources[0].end += BCM_6348_RSET_SPI_SIZE - 1;

		spi_pdata.fifo_size = SPI_6348_MSG_DATA_SIZE;

		spi_pdata.msg_type_shift = SPI_6348_MSG_TYPE_SHIFT;

		spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;

	}



	if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {

arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h

+2 −8
Original line number Diff line number Diff line
@@ -72,18 +72,12 @@ static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) 


	return bcm63xx_regs_spi[reg];

#else

#ifdef CONFIG_BCM63XX_CPU_6338

	__GEN_SPI_RSET(6338)

#endif

#ifdef CONFIG_BCM63XX_CPU_6348

#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)

	__GEN_SPI_RSET(6348)

#endif

#ifdef CONFIG_BCM63XX_CPU_6358

#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6368)

	__GEN_SPI_RSET(6358)

#endif

#ifdef CONFIG_BCM63XX_CPU_6368

	__GEN_SPI_RSET(6368)

#endif

#endif

	return 0;

}

arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

+2 −38
Original line number Diff line number Diff line
@@ -1223,24 +1223,7 @@ 
 * _REG relative to RSET_SPI

 *************************************************************************/



/* BCM 6338 SPI core */

#define SPI_6338_CMD			0x00	/* 16-bits register */

#define SPI_6338_INT_STATUS		0x02

#define SPI_6338_INT_MASK_ST		0x03

#define SPI_6338_INT_MASK		0x04

#define SPI_6338_ST			0x05

#define SPI_6338_CLK_CFG		0x06

#define SPI_6338_FILL_BYTE		0x07

#define SPI_6338_MSG_TAIL		0x09

#define SPI_6338_RX_TAIL		0x0b

#define SPI_6338_MSG_CTL		0x40	/* 8-bits register */

#define SPI_6338_MSG_CTL_WIDTH		8

#define SPI_6338_MSG_DATA		0x41

#define SPI_6338_MSG_DATA_SIZE		0x3f

#define SPI_6338_RX_DATA		0x80

#define SPI_6338_RX_DATA_SIZE		0x3f



/* BCM 6348 SPI core */

/* BCM 6338/6348 SPI core */

#define SPI_6348_CMD			0x00	/* 16-bits register */

#define SPI_6348_INT_STATUS		0x02

#define SPI_6348_INT_MASK_ST		0x03
@@ -1257,7 +1240,7 @@ 
#define SPI_6348_RX_DATA		0x80

#define SPI_6348_RX_DATA_SIZE		0x3f



/* BCM 6358 SPI core */

/* BCM 6358/6368 SPI core */

#define SPI_6358_MSG_CTL		0x00	/* 16-bits register */

#define SPI_6358_MSG_CTL_WIDTH		16

#define SPI_6358_MSG_DATA		0x02
@@ -1274,23 +1257,6 @@ 
#define SPI_6358_MSG_TAIL		0x709

#define SPI_6358_RX_TAIL		0x70B



/* BCM 6358 SPI core */

#define SPI_6368_MSG_CTL		0x00	/* 16-bits register */

#define SPI_6368_MSG_CTL_WIDTH		16

#define SPI_6368_MSG_DATA		0x02

#define SPI_6368_MSG_DATA_SIZE		0x21e

#define SPI_6368_RX_DATA		0x400

#define SPI_6368_RX_DATA_SIZE		0x220

#define SPI_6368_CMD			0x700	/* 16-bits register */

#define SPI_6368_INT_STATUS		0x702

#define SPI_6368_INT_MASK_ST		0x703

#define SPI_6368_INT_MASK		0x704

#define SPI_6368_ST			0x705

#define SPI_6368_CLK_CFG		0x706

#define SPI_6368_FILL_BYTE		0x707

#define SPI_6368_MSG_TAIL		0x709

#define SPI_6368_RX_TAIL		0x70B



/* Shared SPI definitions */



/* Message configuration */
@@ -1298,10 +1264,8 @@ 
#define SPI_HD_W			0x01

#define SPI_HD_R			0x02

#define SPI_BYTE_CNT_SHIFT		0

#define SPI_6338_MSG_TYPE_SHIFT		6

#define SPI_6348_MSG_TYPE_SHIFT		6

#define SPI_6358_MSG_TYPE_SHIFT		14

#define SPI_6368_MSG_TYPE_SHIFT		14



/* Command */

#define SPI_CMD_NOOP			0x00

CRA Git | Maintained and supported by SUSTech CRA and CCSE